High breakdown voltage LDMOS device
A multi-region ( 81, 83 ) lateral-diffused-metal-oxide-semiconductor (LDMOS) device ( 40 ) has a semiconductor-on-insulator (SOI) support structure ( 21 ) on or over which are formed a substantially symmetrical, laterally internal, first LDMOS region ( 81 ) and a substantially asymmetric, laterally edge-proximate, second LDMOS region ( 83 ). A deep-trench isolation (DTI) wall ( 60 ) substantially laterally terminates the laterally edge-proximate second LDMOS region ( 83 ). Electric field enhancement and lower source-drain breakdown voltages (BVDSS) exhibited by the laterally edge-proximate second LDMOS region ( 83 ) associated with the DTI wall ( 60 ) are avoided by providing a doped SC buried layer region ( 86 ) in the SOI support structure ( 21 ) proximate the DTI wall ( 60 ), underlying a portion of the laterally edge-proximate second LDMOS region ( 83 ) and of opposite conductivity type than a drain region ( 31 ) of the laterally edge-proximate second LDMOS region ( 83 ).
1. A multi-gate lateral-diffused-metal-oxide-semiconductor (LDMOS) device comprising:
a semiconductor-on-insulator (SOI) support structure on or over which are located a substantially symmetrical internal LDMOS region and an asymmetric edge-proximate LDMOS region;
a deep-trench isolation (DTI) wall extending into the support structure and terminating the edge-proximate LDMOS region;
a first source region of a first conductivity type in the asymmetric edge-proximate LDMOS region;
a first drain region of the first conductivity type in the asymmetric edge-proximate LDMOS region; and
a doped semiconductor (SC) buried layer (BL) region proximate the DTI wall, underlying a portion of the asymmetric edge-proximate LDMOS region, and of opposite conductivity type than the first drain region of the asymmetric edge-proximate LDMOS region;
wherein the substantially symmetrical internal LDMOS region and the asymmetric edge-proximate LDMOS region are separated by a vertical boundary extending into the multi-gate LDMOS device at a location laterally adjacent the first source region.
2. The LDMOS device of claim 1 , wherein the asymmetric edge-proximate LDMOS region comprises;
a first well region and drift space of the first conductivity type proximate and underlying the drain region;
a second well region of a second, opposite conductivity type, underlying the first well region and drift space; and
wherein the BL region is of the second conductivity type and underlies the second well region proximate the DTI wall.
3. The LDMOS device of claim 2 , wherein the support structure comprises a substrate on which is an insulating layer over which is a first SC layer and further comprising a second SC layer overlying the first SC layer and in which the first and second well regions are substantially located, and wherein the BL region extends substantially from the second well region to the insulating layer.
4. The LDMOS device of claim 1 , wherein the substantially symmetrical internal LDMOS region comprises:
at least one drain region substantially centrally located between a first laterally leftward located source region and a second laterally rightward located source region, the first source region located in a first body region and the second source region located in a second body region separated from the first body region;
a first gate structure extending over at least a first part of the first body region between the first source region and the at least one drain region; and
a second gate structure extending over at least a second part of the second body region between the second source region and the at least one drain region.
5. The LDMOS device of claim 1 , wherein the support structure comprises a substrate on which is an insulating layer over which is a first SC layer and further comprising a second SC layer overlying the first SC layer and having the upper surface.
6. The LDMOS device of claim 5 , wherein the substantially symmetrical internal LDMOS region and the asymmetric edge-proximate LDMOS region are substantially located in the second SC layer.
7. The LDMOS device of claim 5 , wherein the BL region substantially penetrates through the first and second SC layers to the insulating layer.
8. The LDMOS device of claim 5 , wherein the DTI wall penetrates substantially from the upper surface to or through the insulating layer.
9. The LDMOS device of claim 1 , wherein the substantially symmetrical internal LDMOS region has a first drain region fed by at least two source regions located on laterally opposite sides of the first drain region and the asymmetric edge-proximate LDMOS region has a least one second drain region fed by the first source region located laterally only on one side of the second drain region.
10. A multi-gate lateral-diffused-metal-oxide-semiconductor (LDMOS) device comprising:
a first LDMOS region having a first source region and a first drain region about which the first LDMOS region is substantially symmetrical;
a deep-trench isolation (DTI) wall formed adjacent a sidewall edge of the LDMOS device;
a second LDMOS region having a second source region and a second drain region about which the second LDMOS region is asymmetrical, the second LDMOS region located between the first LDMOS region and the DTI wall, the first and second LDMOS regions separated by a vertical boundary, which extends into the multi-gate LDMOS device at a location laterally adjacent the second source region of the second LDMOS device; and
a doped semiconductor (SC) buried layer (BL) region underlying the second LDMOS region and located proximate a juncture between the second LDMOS region and the DTI wall, the doped SC having a conductivity type opposite that of the second drain region and increasing the breakdown voltage of the second LDMOST region during operation of the LDMOS device.
11. The LDMOS device of claim 10 further comprising a semiconductor-on-insulator (SOI) support structure on which or over which the first and second LDMOS regions are formed;
wherein the SOI support structure comprises a buried oxide layer, and wherein the doped SC BL region is formed between the buried oxide layer and the second LDMOST region.
12. The LDMOS device of claim 11 , wherein the SOI support structure comprises an SC layer overlying the buried oxide layer, and wherein the doped SC BL region is formed in the SC layer.
13. The LDMOS device of claim 12 , wherein the doped SC BL region extends through the SC layer to the buried oxide layer.
14. The LDMOS device of claim 11 , wherein the DTI wall intersects the doped SC BL region.