Semiconductor device with group-III nitride compound semiconductor layer on substrate for transistor
To realize a transistor of normally-off type having a high mobility and a high breakdown voltage. A compound semiconductor layer is formed over a substrate, has both a concentration of p-type impurities and a concentration of n-type impurities less than 1×10 16 /cm 3 , and includes a group III nitride compound. A well is a p-type impurity layer and formed in the compound semiconductor layer. A source region is formed within the well and is an n-type impurity layer. A low-concentration n-type region is formed in the compound semiconductor layer and is linked to the well. A drain region is formed in the compound semiconductor layer and is located on a side opposite to the well via the low-concentration n-type region. The drain region is an n-type impurity layer.
1. A semiconductor device comprising:
a substrate;
a compound semiconductor layer that is formed over the substrate, that has both the concentration of p-type impurities and the concentration of n-type impurities being less than 1×10 16 /cm 3 , and that includes a group III nitride compound;
a p-type well that is formed in the compound semiconductor layer;
a source region that is formed in the compound semiconductor layer and that is an n-type impurity layer;
a low-concentration n-type region that is formed in the compound semiconductor layer and that is linked to the well;
a drain region that is formed in the compound semiconductor layer, that is located on a side opposite to the well via the low-concentration n-type region, and that is an n-type impurity layer;
a gate insulating film that is formed over a portion of the well located between the source region and the low-concentration n-type region; and
a gate electrode that is formed over the gate insulating film.
2. The semiconductor device according to claim 1 ,
wherein the source region is formed within the well.
3. The semiconductor device according to claim 1 , comprising
a high-resistance compound semiconductor layer that is located between the substrate and the compound semiconductor layer and that has a sheet resistance higher than that of the compound semiconductor layer.
4. The semiconductor device according to claim 3 , comprising
a buffer layer located between the high-resistance compound semiconductor layer and the substrate.
5. The semiconductor device according to claim 1 , comprising
a p-type compound semiconductor layer that is formed under the compound semiconductor layer and that has an impurity concentration higher than that of the well,
wherein a lower part of the well and a lower part of the drain region are located within the p-type compound semiconductor layer.
6. The semiconductor device according to claim 1 ,
wherein the impurity concentration of the well is 1×10 16 cm −3 or more and 1×10 19 cm −3 or less.
7. The semiconductor device according to claim 1 , comprising:
an insulating layer formed over the low-concentration n-type region; and
a field plate electrode formed over the insulating layer.
8. The semiconductor device according to claim 1 ,
wherein the compound semiconductor layer is a nitride gallium layer.
9. The semiconductor device according to claim 1 ,
wherein the impurity concentration of the low-concentration n-type region is 1×10 16 cm −3 or more and 1×10 19 cm −3 or less, and
wherein the impurity concentration of the drain region is 1×10 19 cm −3 or more and 1×10 22 cm −3 or less.