Semiconductor integrated circuit, method for fabricating the same, and semiconductor package
A semiconductor integrated circuit device includes a TSV (Through Silicon Via) extending through a substrate, a first well in the substrate adjacent a first surface of the substrate, a gate of an active device on the first well, a charging protection well, and a charging protection gate on the charging protection well. The charging protection well is disposed in the substrate adjacent the first surface of the substrate, is interposed between the TSV hole and the first well, and surrounds the TSV hole. The charging protection gate prevents the gate of the active device from being damaged when the TSV is formed especially when using a plasma etch process to form a TSV hole in the substrate.
1. A semiconductor integrated circuit device comprising:
a substrate that has a first outer surface and a second outer surface, and a TSV (through silicon via) hole extending therethrough between the first outer surface and the second outer surface;
a TSV contact in the TSV hole;
a first well in the substrate and having a surface contiguous with the first outer surface of the substrate;
a first gate of an active device on the first well;
a charging protection well in the substrate, interposed between the TSV hole and the first well as spaced in the substrate from the first well, having a surface contiguous with the first outer surface of the substrate, and surrounding the TSV hole; and
a charging protection gate on the charging protection well, and
wherein the charging protection gate is a dummy gate electrically isolated from the active device.
2. The semiconductor integrated circuit device of claim 1 , wherein the charging protection gate is spaced apart from the TSV hole.
3. The semiconductor integrated circuit device of claim 1 , wherein the charging protection gate comprises:
a charging protection gate dielectric layer on the charging protection well; and
a charging protection gate electrode on the charging protection gate dielectric layer.
4. The semiconductor integrated circuit device of claim 3 , wherein the first gate comprises:
a gate dielectric layer on the first well; and
a gate electrode on the gate dielectric layer.
5. The semiconductor integrated circuit device of claim 1 , further comprising:
an interlayer insulating layer covering the charging protection gate and the first gate on the substrate; and
a plurality of wiring patterns disposed on the interlayer insulating layer,
wherein the plurality of wiring patterns are electrically connected to the TSV electrode and the first well.
6. The semiconductor integrated circuit device of claim 5 , wherein the TSV hole and the TSV electrode extend through the interlayer insulating layer.
7. The semiconductor integrated circuit device of claim 1 , further comprising a field insulating layer surrounding the TSV hole and interposed between the TSV hole and the charging protection well.
8. The semiconductor integrated circuit device of claim 1 , wherein a side wall surface of the charging protection well delimits part of the TSV hole.
9. The semiconductor integrated circuit device of claim 8 , further comprising a field insulating layer surrounding the TSV hole and disposed in the charging protection well, and
wherein a side wall of the field insulating layer delimits part of the TSV hole.
10. The semiconductor integrated circuit device of claim 1 , wherein the charging protection gate has a plurality of discrete segments spaced apart from each other along the charging protection well.
11. The semiconductor integrated circuit device of claim 10 , wherein each of the plurality of segments of the charging protection gate is disposed the same distance from the TSV hole as the others of the segments.
12. The semiconductor integrated circuit device of claim 1 , wherein the charging protection gate surrounds the TSV hole.
13. A semiconductor integrated circuit device comprising:
a substrate that has a first surface and a second surface;
a TSV (through silicon via) extending through substrate between the first surface and the second surface;
a first well in the substrate at the first surface, the well having one of a P-type and N-type conductivity;
a transistor including a gate electrode, and a gate dielectric layer extending between the first well and the gate electrode;
a charging protection well in the substrate and interposed between the TSV and the first well as spaced in the substrate from the first well, the charging protection well having the same type of conductivity as the first well; and
a charging protection structure, wherein the charging protection structure comprises a protection dielectric layer on the charging protection well, and an electrically conductive layer disposed directly on the dielectric layer so as to have the form of a gate,
wherein the electrically conductive layer of the charging protection structure is a dummy layer electrically isolated from the transistor.
14. The semiconductor integrated circuit device of claim 13 , wherein the charging protection well surrounds the TSV.
15. The semiconductor integrated circuit device of claim 13 , further comprising an interlayer insulating layer disposed on the first surface of the substrate, and wherein the charging protection structure and the interlayer insulating layer together cover the charging protection well in its entirety.
16. The semiconductor integrated circuit device of claim 15 , further comprising a contact extending through the interlayer insulating layer to the transistor, and wiring disposed on the interlayer insulating layer, wherein the wiring electrically connects the contact and the TSV and is electrically isolated from the charging protections structure.
17. A semiconductor package comprising:
a package substrate;
a first semiconductor integrated circuit device disposed on the package substrate; and
a second semiconductor integrated circuit device disposed on the first semiconductor integrated circuit device,
wherein the first semiconductor integrated circuit device includes:
a device substrate that has a first outer surface and a second outer surface, and a TSV (through silicon via) hole extending therethrough between the first outer surface and the second outer surface,
a TSV contact in the TSV hole,
a first well in the device substrate and having a surface contiguous with the first outer surface of the device substrate,
a first gate of an active device on the first well,
a charging protection well in the device substrate, interposed between the TSV hole and the first well as spaced in the device substrate from the first well, having a surface contiguous with the first outer surface of the device substrate, and surrounding the TSV hole, and
a charging protection gate on the charging protection well, and
wherein the charging protection gate is a dummy gate electrically isolated from the active device.
18. The semiconductor package of claim 17 , wherein the first semiconductor integrated circuit device further comprises a field insulating layer surrounding the TSV hole and interposed between the TSV hole and at least part of the charging protection well.