Printed-circuit board supporting memory systems with multiple data-bus configurations
Described is a printed-circuit board (PCB) that supports memory systems in which the memory core organization changes with device width. The PCB includes a memory-controller mounting location and module connectors to receive respective memory modules. Each module connector connects directly to the controller mounting location via a respective set of system data lines that does not connect to any other module connector. System data lines also extend directly between module connectors to support memory configurations with different numbers of modules. The memory systems support one memory module of a wide data width or multiple memory modules of narrower data widths. The number of physical memory banks accessed reduces with device data width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logic memory banks for narrow memory widths reduces the likelihood of bank conflicts, and consequently improves speed performance.
1. A printed-circuit board comprising:
a circuit mounting location for an integrated circuit comprising a memory controller;
a first module connector on the printed-circuit board, the first module connector to accept a first memory module having a first data bus width, the first data bus width specifying a first number of data bit lines;
a second module connector on the printed-circuit board, the second module connector to accept a second memory module having the first data bus width;
a first set of system data lines, fewer than the first number of data bit lines, extending directly to the first module connector from the circuit mounting location without connection to the second module connector;
a second set of system data lines, fewer than the first number of data bit lines, extending directly to the second module connector from the circuit mounting location without connection to the first module connector; and
a third set of system data lines, fewer than the first number of data bit lines, extending directly to the first module connector from the second module connector without connection to the circuit mounting location.
2. The printed-circuit board of claim 1 , further comprising a continuity module inserted in the second module connector to connect each line in the second set of system data lines to a respective line in the third set of system data lines.
3. The printed-circuit board of claim 2 , wherein the first number of data bit lines consists of the first and third sets of system data lines together comprise the first data bus width.
4. The printed-circuit board of claim 1 , further comprising a third module connector on the printed-circuit board, the third module connector to accept an optional third memory module.
5. The printed-circuit board of claim 4 , further comprising a fourth set of system data lines, less than the first data bus width, extending directly to the third module connector from the circuit mounting location without connection to the first module connector or the second module connector.
6. The printed-circuit board of claim 5 , further comprising a fifth set of system data lines, less than the first data bus width, extending directly from the second module connector to the third module connector.
7. The printed-circuit board of claim 1 , wherein the third set of system data lines includes the same number of signal lines as at least one of the first set of system data lines and the second set of system data lines.
8. The printed-circuit board of claim 1 , further comprising address and control lines extending from the circuit mounting location to each of the first module connector and the second module connector.
9. A memory system comprising:
a printed-circuit board having a circuit mounting location for an integrated circuit, the integrated circuit including a memory controller;
a first module connector on the printed-circuit board, the first module connector to receive a memory module;
a second module connector on the printed-circuit board;
sets of system data lines, each set extending directly from the circuit mounting location to a different one of the first module connector and the second module connector, the sets of system data lines including:
a first set of system data lines extending from the circuit mounting location directly to the first module connector; and
a second set of system data lines extending from the circuit mounting location directly to the second module connector;
a third set of system data lines extending directly from the first module connector to second module connector; and
shorting conductors in the second module connector and interconnecting each data line of the second set of system data lines with a corresponding data line of the third set of system data lines.
10. The memory system of claim 9 , further comprising a third module connector on the printed circuit board, the sets of system data lines further including a fourth set of system data lines extending from the circuit mounting location directly to the third module connector.
11. The memory system of claim 9 , further comprising a memory module installed in the first module connector, the memory module having a first side connected to the circuit mounting location via the first set of system data lines and a second side connected to the circuit mounting location via the third set of system data lines, the shorting conductors, and the second set of system data lines.
12. The memory system of claim 9 , wherein the shorting conductors extend through a shorting module.
13. The memory system of claim 9 , wherein the first, second, and third sets of system data lines are point-to-point connections.
14. The memory system of claim 9 , wherein the third set of system data lines includes the same number of data lines as at least one of the first and second sets of system data lines.
15. The memory system of claim 9 , further comprising the memory module, the memory module supporting a first data-width configuration to communicate via both of the first and second sets of system data lines and a second data-width configuration to communicate via only one of the first and second sets of system data lines.