Integrated high-k/metal gate in CMOS process flow

1. A semiconductor device comprising:

a semiconductor substrate that has a first-type active region and a second-type active region;

a first dielectric layer over the semiconductor substrate, the first dielectric layer having a trench formed therein, the trench being over both the first-type active region and the second-type active region;

a second dielectric layer over the semiconductor substrate within the trench;

a first metal layer having a first work function formed over the second dielectric layer, the first metal layer being at least partially removed from over the second-type active region;

a second metal layer over the first metal layer in the first-type active region and over the second dielectric layer in the second-type active region, the second metal layer having a second work function.

2. The semiconductor device of claim 1 in which the first-type active region comprises an NMOS active region, and in which the second-type active region comprises a PMOS active region.

3. The semiconductor device of claim 1 in which an NMOS gate stack of the semiconductor device includes the second dielectric layer, the first metal layer, and the second metal layer, and in which a PMOS gate stack of the semiconductor device includes the second dielectric layer and the second metal layer.

4. The semiconductor device of claim 3 in which the NMOS gate stack has a different metal thickness than that of the PMOS gate stack.

5. The semiconductor device of claim 1 in which the second metal layer does not affect the first work function.

6. The semiconductor device of claim 1 further comprising a shallow trench isolation (STI) between the NMOS active region and the PMOS active region.

7. The semiconductor device of claim 1 further comprising a third metal layer over the second metal layer in the first-type active region and over the second metal layer in the second-type active region, in which the second metal layer has a thickness smaller than a thickness of the third metal layer.

8. A semiconductor device comprising:

a semiconductor substrate that has a first type active region adjacent a second type active region;

a dielectric layer over the semiconductor substrate;

a first metal layer overlying the first type active region, the first metal layer having a first work function; and

a first portion of a second metal layer overlying the first metal layer in the first type active region and a second portion of the second metal layer overlying the dielectric layer in the second type active region, a top surface of the second portion being lower than a bottom surface of the first portion, the second metal layer having a second work function that is different than the first work function.

9. The semiconductor device of claim 8 further comprising:

a third metal layer overlying the second metal layer in the first type active region and overlying the second metal layer in the second type active region; and

a barrier metal layer and a filler metal layer over the third metal layer.

10. The semiconductor device of claim 9 in which the second metal layer has a thickness smaller than a thickness of the third metal layer.

11. The semiconductor device of claim 9 , further comprising, an interlayer dielectric (ILD) layer over the substrate, the ILD layer comprising a trench over the first type active region and the second type active region.

12. The semiconductor device of claim 9 , wherein the second metal layer is within the trench and the third metal layer is within the trench.

13. The semiconductor device of claim 8 , wherein a shallow trench isolation (STI) between the first type active region and the second type active region, and wherein the first type active region is an NMOS active region and the second type active region is a PMOS active region.

14. A semiconductor device comprising:

a semiconductor substrate that has a first-type active region and a second-type active region;

a first dielectric layer over the substrate, the first dielectric layer comprising a trench over the first-type active region and the second-type active region;

a second dielectric layer over the semiconductor substrate;

a first metal layer having a first work function formed over the second dielectric layer in both the first-type active region and the second-type active region;

a second metal layer over the first metal layer in the first-type active region, the second metal layer having a second work function; and

a third metal layer over the second metal layer in the first-type active region.

15. The semiconductor device of claim 14 in which the first metal in the first-type active region is of a thickness that causes the first metal not to affect the second work function.

16. The semiconductor device of claim 15 in which the first metal layer comprises TaN, wherein the second metal layer comprises TiN, and wherein the third metal layer comprises WN or TiN and in which the third metal layer has a third work function, wherein the first and third work functions are different from the second work function.

17. The semiconductor device of claim 15 in which the first-type active region comprises an NMOS active region, and in which the second-type active region comprises a PMOS active region.

18. The semiconductor device of claim 15 further comprising a barrier metal layer and a filler metal layer over the third metal layer.

19. The semiconductor device of claim 15 further comprising an STI between the first-type active region and the second-type active region.

20. The semiconductor device of claim 15 further comprising a first capping layer over the first-type active region and a second capping layer over the second-type active region, the first and second capping layers being made of different materials.