IP Library › Granted Patent US 9,269,612
Granted Patent B2
US 9,269,612 · App. 13/434,691 · Granted Feb 23, 2016

Mechanisms of forming damascene interconnect structures

Inventors: Chien-An Chen (Zhubei, TW); Wen-Jiun Liu (Zhunan Township, TW); Chun-Chieh Lin (Taichung, TW); Hung-Wen Su (Jhubei, TW); Ming-Hsing Tsai (Chu-Pei, TW); Syun-Ming Jang (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H01L21/76819H01L21/76834H01L21/76847H01L21/76849H01L21/76864H01L21/76882H01L23/53238H01L2924/0002
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Quick Facts
Patent No.
US 9,269,612
App. No.
13/434,691
Granted
Feb 23, 2016
Kind
B2
Abstract

An interconnect structure includes a first trench and a second trench. The second trench is wider than the first trench. Both trenches are lined with a diffusion barrier layer, and a first conductive layer is deposited over the diffusion barrier layer. A metal cap layer is deposited over the first conductive layer. A second conductive layer is deposited over the metal cap layer in the second trench.

Claims (34)

1. An interconnect structure, comprising:

a first trench; and

a second trench, wherein the second trench is wider than the first trench, and wherein both trenches are lined with a diffusion barrier layer having a substantially uniform thickness, and wherein a first conductive layer is deposited over the diffusion barrier layer, and wherein a metal cap layer is over the first conductive layer, and wherein a second conductive layer is deposited over the metal cap layer in the second trench, and the diffusion barrier layer is between the second conductive layer and a sidewall of the second trench, and the metal cap layer inside the second trench is in direct contact with the diffusion barrier layer,

wherein a first maximum thickness of the first conductive layer in the second trench is less than a second maximum thickness of the first conductive layer in the first trench.

2. The interconnect structure of claim 1 , wherein the second conductive layer is over the metal cap layer in the first trench.

3. The interconnect structure of claim 1 , wherein the first conductive layer is thicker in the first trench than the second trench.

4. The interconnect structure of claim 1 , wherein the first conductive layer and the second conductive layer both comprise copper.

5. The interconnect structure of claim 1 , wherein the metal cap layer comprises at least one of cobalt, nickel, tungsten, molybdenum, silicon, zinc, chrome, boron, phosphorus, nitrogen, or combinations thereof.

6. The interconnect structure of claim 1 , wherein the metal cap layer has a thickness in a range from 0.5 nm to 20 nm.

7. The interconnect structure of claim 1 , wherein the width of the first trench is in a range from 10 nm to 100 nm.

8. The interconnect structure of claim 1 , wherein first and second trenches are part of at least one dual damascene structure.

9. The interconnect structure of claim 1 , wherein a distance from a top surface of the second trench to the first conductive layer is in a range from 1 nm to 50 nm.

10. An interconnect structure, comprising:

a first trench; and

a second trench, wherein the second trench is wider than the first trench, and wherein both trenches are lined with a diffusion barrier layer having a substantially uniform thickness, and wherein a conductive layer is over the diffusion barrier layer, and a metal cap layer in both trenches is over an entirety of the conductive layer, and a second conductive layer is over the metal cap layer in the second trench, and the diffusion barrier layer is between the second conductive layer and a sidewall of the second trench,

wherein a first maximum thickness of the first conductive layer in the second trench is different from a second maximum thickness of the first conductive layer in the first trench, and a bottom surface of the first conductive layer in the second trench is substantially co-planar with a bottom surface of the first conductive layer in the first trench.

11. An interconnect structure comprising:

a substrate;

a dielectric layer over the substrate, the dielectric layer having a first opening therein;

a diffusion barrier layer lining the first opening, wherein a top surface of the diffusion barrier layer is planar with a top surface of the dielectric layer, and the diffusion barrier layer has a substantially uniform thickness;

a first conductive layer in the first opening, wherein an entirety of the first conductive layer is below the top surface of the dielectric layer;

a first process layer over the first conductive layer, wherein a top surface of a central portion of the first process layer is below the top surface of the dielectric layer; and

a second conductive layer in the first opening, wherein the first process layer is between the second conductive layer in the first opening and the dielectric layer, wherein a maximum thickness of the second conductive layer in the first opening is greater than a maximum thickness of the second conductive layer in a neighboring trench.

12. The interconnect structure of claim 11 , wherein the second conductive layer in the first opening is over the first process layer, wherein the first process layer is a metal cap layer.

13. The interconnect structure of claim 12 , wherein a top surface of the second conductive layer in the first opening is planar with the top surface of the dielectric layer.

14. The interconnect structure of claim 11 , further comprising:

a second conductive layer in a second opening in the dielectric layer, wherein a top surface of the second conductive layer in the second opening is below the top surface of the dielectric layer; and

a second process layer over the second conductive layer in the second opening.

15. The interconnect structure of claim 14 , wherein a first distance between the top surface of the first conductive layer and the top surface of the dielectric layer is greater than a second distance between the top surface of the second conductive layer in the second opening and the top surface of the dielectric layer.

16. The interconnect structure of claim 14 , wherein the second process layer is a metal cap layer and a top surface of the metal cap layer is planar with the top surface of the dielectric layer.

17. The interconnect structure of claim 14 , wherein the second process layer is a metal cap layer.

18. The interconnect structure of claim 14 , further comprising a third conductive layer over the second process layer, wherein the second process layer is a metal cap layer.

19. The interconnect structure of claim 18 , wherein a top surface of the third conductive layer is planar with the top surface of the dielectric layer.

20. The interconnect structure of claim 11 , wherein the diffusion barrier layer is between a sidewall of the first process layer and the dielectric layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2012
From: CHEN, CHIEN-AN; LIU, WEN-JIUN; LIN, CHUN-CHIEH; SU, HUNG-WEN; TSAI, MING HSING; JANG, SYUN-MING
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 027959/0424 →
Continuity (2)
Provisional Application 61562705 · Nov 22, 2011
Related Publication 20130127055A1 · May 23, 2013