Cell pillar structures and integrated flows
Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.
1. An apparatus, comprising:
a source material;
a drain-side select gate (SGD);
a memory stack arranged between the source material and the SGD and having alternating levels of conductor materials and dielectric materials between a level corresponding to the source material and a level corresponding to the SGD; and
a channel-fill material that is continuous from the source material to at least the level corresponding to the SGD, the memory stack including a plurality of recessed charge storage structures, a substantial amount of each of the plurality of charge storage structures being formed within a level of respective ones of the conductor material and laterally away from the channel-fill material, each of the plurality of charge storage structures further being formed substantially between adjacent ones of the alternating levels of dielectric materials with each of the plurality of recessed charge storage structures being separated from a remaining portion of the conductor material on the same level by a dielectric material.
2. The apparatus of claim 1 , wherein the channel-fill material forms a cell pillar.
3. The apparatus of claim 1 , further comprising:
a source-side select gate (SGS) formed between the level corresponding to the source material and the memory stack; and
an etch stop formed between a level corresponding to the SGS and the level corresponding to the source material.
4. The apparatus of claim 3 , wherein the etch stop is formed from a dielectric material having a high dielectric constant.
5. The apparatus of claim 3 , wherein the etch stop comprises aluminum oxide.
6. The apparatus of claim 1 , wherein the source material includes a transition metal combined with a semiconductor material.
7. The apparatus of claim 1 , wherein the source material comprises tungsten silicide.
8. The apparatus of claim 1 , further comprising a buffer material formed between the level corresponding to the source material and the memory stack.
9. The apparatus of claim 1 , wherein the conductor material comprises a semiconductor material.
10. the apparatus of claim 9 , wherein the semiconductor material comprises a conductively-doped polysilicon.
11. A method of forming a memory apparatus, the method comprising:
forming a source material;
forming a buffer material over the source material;
forming a memory stack over the buffer material, the memory stack comprising alternating levels of conductor materials and dielectric materials;
forming a drain-side select gate (SGD) over the memory stack;
forming a continuous cell pillar from the source material to at least a level corresponding to the SGD; and
etching a portion of respective ones of the conductive materials within the memory stack laterally away from the continuous cell pillar to form a plurality of recessed charge storage structures, each of the plurality of charge storage structures being formed within a level of the respective ones of the conductor material and further being formed substantially between adjacent ones of the alternating levels of dielectric materials.
12. The method of claim 11 , further comprising forming an etch stop over the buffer material, wherein forming a memory stack over the buffer material further comprises forming the memory stack over the etch stop.
13. The method of claim 12 , wherein forming the memory stack includes forming a number of levels of the conductor materials and a number of levels of the dielectric materials, each of the number of levels of the conductor materials being separated from a respective adjacent one of the levels of the conductor materials by at least a respective one of the levels of the dielectric materials.
14. The method of claim 12 , further comprising:
forming a continuous pillar opening from the SGD to at least the etch stop; and
filling the continuous pillar opening with a channel-fill material.
15. The method of claim 12 , wherein forming an etch stop over the buffer material comprises forming a dielectric material having a high dielectric constant over the buffer material.
16. The method of claim 12 , wherein forming an etch stop over the buffer material comprises forming aluminum oxide over the buffer material.
17. The method of claim 11 , wherein forming the source material comprises forming a transition metal combined with a semiconductor material.
18. The method of claim 11 , wherein forming the source material comprises forming tungsten silicide.
19. The method of claim 11 , further comprising forming a continuous pillar opening from the source material to at least a level corresponding to the SGD.
20. The method of claim 19 , wherein forming the continuous pillar opening from the source material to at least a level corresponding to the SGD comprises etching the continuous pillar opening through the memory stack and the buffer material, wherein the source material acts as an etch stop.
21. An apparatus, comprising:
a source material;
an active semiconductor switching device;
a plurality of active devices arranged between the source material and the active semiconductor switching device, alternating levels of semiconductor materials and dielectric materials are between a level corresponding to the active semiconductor switching device and a level corresponding to the source material; and
a channel-fill material that is continuous from the source material to at least the level corresponding to the active semiconductor switching device, the memory stack including a plurality of recessed charge storage structures, a substantial amount of each of the plurality of charge storage structures being formed within a level of respective ones of the semiconductor material and laterally away from the channel-fill material, each of the plurality of charge storage structures further being formed substantially between adjacent ones of the alternating levels of dielectric materials with each of the plurality of recessed charge storage structures being separated from a remaining portion of the semiconductor material on the same level by a dielectric material.
22. The apparatus of claim 21 , wherein the plurality of active devices comprise a memory stack.
23. The apparatus of claim 21 , wherein at least one of the dielectric materials is a solid electrolyte.
24. The apparatus of claim 21 , wherein at least one of the dielectric materials is a chalcogenide.
25. A method comprising:
forming a source material;
forming a buffer material over the source material;
forming at least one active device over the buffer material, the at least one active device comprising at least one conductive material formed between dielectric materials;
forming an active semiconductor switching device over the at least one active device;
forming a continuous pillar opening through the at least one active device and the active semiconductor switching device to the source material;
filling the continuous pillar opening with a channel-fill material; and
etching a portion of the at least one conductive material within the at least one active device laterally away from the continuous pillar to form a recessed structure, the recessed structure being formed within a level of the at least one conductive material and further being formed substantially between adjacent ones of the dielectric materials.
26. The method of claim 25 , further comprising forming an etch stop over the buffer material, wherein forming at least one active device over the buffer material comprises forming at least one active device over the etch stop.
27. The method of claim 25 , wherein forming at least one active device comprises forming a memory cell.
28. The method of claim 25 , wherein forming at least one active device comprises forming a conductive-bridging random-access memory cell.
29. The method of claim 25 , wherein forming the source material comprises forming a transition metal combined with a semiconductor material.