Methods of fabricating semiconductor stack packages

1. A method of fabricating a semiconductor stack package, the method comprising:

preparing an interposer in which a first through electrode is inserted, the first through electrode having a first contact portion exposed at a top surface of the interposer;

vertically stacking a plurality of first semiconductor chips on the top surface of the interposer to form a semiconductor chip stack connected to the first contact portion;

recessing a bottom surface of the interposer to expose a second contact portion of the first through electrode opposite to the first contact portion; and

stacking a second semiconductor chip on a bottom surface of the interposer to connect the second semiconductor chip to the second contact portion of the first through electrode,

wherein recessing the bottom surface of the interposer includes grinding, chemically and mechanically polishing or etching back the bottom surface of the interposer to expose a second contact portion of the first through electrode opposite to the first contact portion.

2. The method of claim 1 , wherein preparing the interposer includes:

forming a groove that extends from the top surface of the interposer into a bulk region of the interposer; and

filling the groove with a conductive material to form a first through electrode.

3. The method of claim 1 , wherein the semiconductor chip stack is formed to include a second through electrode that penetrates the plurality of first semiconductor chips to electrically connect the first semiconductor chips to each other, and the second through electrode is electrically connected to the first contact portion.

4. The method of claim 1 , wherein stacking the plurality of first semiconductor chips includes:

preparing the plurality of first semiconductor chips, so that each of the first semiconductor chips being formed to include a partial through electrode penetrating a body thereof; and

sequentially stacking the plurality of first semiconductor chips on the interposer to electrically connect the partial through electrodes to each other,

wherein the partial through electrodes constitute a second through electrode.

5. The method of claim 1 , wherein stacking the plurality of first semiconductor chips includes:

preparing the plurality of first semiconductor chips, so that each of the first semiconductor chips being formed to include a partial through electrode penetrating a body thereof;

sequentially stacking the plurality of first semiconductor chips to electrically connect the partial through electrodes to each other and to form a semiconductor chip stack; and

stacking the semiconductor chip stack on the interposer.

6. The method of claim 1 , wherein recessing the bottom surface of the interposer further includes additionally recessing the bottom surface of the interposer such that a lower portion of the first through electrode protrudes from the recessed bottom surface of the interposer.

7. The method of claim 1 , further comprising forming a first protection layer that covers the semiconductor chip stack, before the bottom surface of the interposer is recessed.

8. The method of claim 1 , wherein the second semiconductor chip includes a third through electrode electrically connected to the second contact portion of the first through electrode.

9. The method of claim 1 , further comprising:

forming a second protection layer that covers the second semiconductor chip; and

removing a portion of the second protection layer to form an opening that exposes a portion of the second semiconductor chip.

10. The method of claim 9 , further comprising attaching an external electrode to the second semiconductor chip exposed by the opening.

11. The method of claim 1 , further comprising forming a second protection layer that leaves exposed a surface of the second semiconductor chip opposite to the interposer and covers sidewalls of the second semiconductor chip.

12. A method of fabricating a semiconductor stack package, the method comprising:

preparing an interposer in which first through electrodes are inserted, each of the first through electrodes having a first contact portion exposed at a top surface of the interposer;

stacking a plurality of semiconductor chip stacks electrically connected to the first contact portions on the top surface of the interposer to be laterally spaced apart from each other;

forming a first protection layer that fills an empty space between the semiconductor chip stacks;

recessing a bottom surface of the interposer to expose second contact portions of the first through electrodes opposite to the first contact portions;

stacking a plurality of second semiconductor chips electrically connected to the second contact portions on a bottom surface of the interposer opposite to the semiconductor chip stacks; and

removing a portion of the first protection layer between the semiconductor chip stacks and a portion of the interposer to separate a substrate including the semiconductor chip stacks and the second semiconductor chips into a plurality of semiconductor stack packages,

wherein each of the semiconductor stack packages includes one of the semiconductor chip stacks, one of the second semiconductor chips, and a portion of the interposer between the semiconductor chip stack and the second semiconductor chip.