Non-volatile random access memory devices with shared transistor configuration and methods of forming the same
Embodiments of non-volatile random access memory (RAM) devices and methods of forming the same are provided herein. In an embodiment, a non-volatile RAM device includes a first access transistor that is in electrical communication with a wordline. A first memory element and a first two-terminal selector are serially connected to each other and are in electrical communication with a first bitline and the first access transistor. A second memory element and a second two-terminal selector are serially connected to each other and are in electrical communication with a second bitline and the first access transistor.
1. A non-volatile random access memory device comprising:
a first access transistor in electrical communication with a wordline;
a first memory element and a first two-terminal selector serially connected and in electrical communication with a first bitline and the first access transistor, wherein the first two-terminal selector is disposed between the first memory element and the first bitline; and
a second memory element and a second two-terminal selector serially connected and in electrical communication with a second bitline and the first access transistor, wherein the second two-terminal selector is disposed between the second memory element and the second bitline.
2. The non-volatile random access memory device of claim 1 , wherein the first memory element and the second memory element share a connection to the first access transistor.
3. The non-volatile random access memory device of claim 1 , wherein the first memory element and the second memory element comprise a first magnetic tunneling junction and a second magnetic tunneling junction, respectively.
4. The non-volatile random access memory device of claim 3 , wherein the first magnetic tunneling junction and the second magnetic tunneling junction each form a 1-transistor-1-magnetic tunneling junction cell with the first access transistor.
5. The non-volatile random access memory device of claim 1 , wherein the first memory element and the second memory element comprise a first resistor and a second resistor, respectively.
6. The non-volatile random access memory device of claim 5 , wherein the first resistor and the second resistor each form a 1-transistor-1-resistor junction cell with the first access transistor.
7. The non-volatile random access memory device of claim 1 , wherein the first two-terminal selector and the second two-terminal selector are non-linear selectors.
8. The non-volatile random access memory device of claim 7 , wherein the first two-terminal selector and the second two-terminal selector are diode selectors.
9. The non-volatile random access memory device of claim 8 , wherein the first two-terminal selector and the second two-terminal selector are chosen from p-n junctions and metal Schottky junctions.
10. The non-volatile random access memory device of claim 7 , wherein the first two-terminal selector and the second two-terminal selector are bidirectional selectors.
11. The non-volatile random access memory device of claim 10 , wherein the first two-terminal selector and the second two-terminal selector are chosen from varistors or metal-insulator-metal elements.
12. The non-volatile random access memory device of claim 1 , further comprising from 1 to about 50 additional memory element and two-terminal selector pairs serially connected and in electrical communication with a respective bitline and the first access transistor.
13. The non-volatile random access memory device of claim 1 , wherein the first access transistor is a shared access transistor of a shared access transistor array.
14. The non-volatile random access memory device of claim 1 , wherein the first access transistor is a wordline access transistor of a crossbar array.