Integrated circuit and method of detecting a data integrity error
An integrated circuit comprises a write bus coupled to a register for storing control data. A storage unit is arranged to store reference signature data encoding a reference collective state of the register. First logic circuitry generates actual signature data encoding the actual collective state of the register. Second logic circuitry is coupled to the storage unit, receives the actual signature data and compares the actual signature data with the reference signature data. The second logic circuitry comprises an alert output to provide an alert signal in response to the comparison identifying a difference between the actual signature data and the reference signature data, thereby ensuring detection of a data integrity error in respect of the register. An alert inhibitor comprises a control input and is responsive to the control input and arranged to inhibit selectively onward propagation of the alert signal from the alert output.
1. An integrated circuit comprising:
a write bus operably coupled to a register for storing control data;
a storage unit arranged to store reference signature data encoding a reference collective state of the register;
first logic circuitry arranged to generate actual signature data encoding the actual collective state of the register;
second logic circuitry operably coupled to the storage unit and arranged to receive the actual signature data and compare the actual signature data with the reference signature data stored by the storage unit; and
an alert inhibitor; wherein
the second logic circuitry comprises an alert output to provide thereat an alert signal in response to the comparison identifying a difference between the actual signature data and the reference signature data, thereby ensuring detection of a data integrity error in respect of the register; and
the alert inhibitor comprises a control input, the alert inhibitor being responsive to the control input and arranged to inhibit selectively onward propagation of the alert signal from the alert output.
2. A circuit as claimed in claim 1 , further comprising:
third logic circuitry hardwired to encode the reference signature data in response to and based upon a number of data bits to be written to the register.
3. A circuit as claimed in claim 2 , wherein:
the write bus comprises a plurality of data lines respectively coupled at one end thereof to bits of the register; and
the third logic circuitry is operably coupled to the plurality of data lines in order to receive the data bits to be written to the register.
4. A circuit as claimed in claim 2 , wherein the third logic circuitry is arranged to generate the reference signature data prior to generation of the actual signature data.
5. A circuit as claimed in claim 1 , wherein the first logic circuitry is hardwired to encode the actual signature data using data bits stored in the register.
6. A circuit as claimed in claim 5 , wherein the first logic circuitry is operably coupled to the storage unit arranged to generate the reference signature data using a number of the data bits stored in the register, the reference signature data generated by the first logic circuitry being stored by the storage unit in response to writing the control data to the register.
7. A circuit as claimed in claim 1 , wherein the first logic circuitry is arranged to encode the actual signature data in accordance with an error detection coding scheme.
8. A circuit as claimed in claim 7 , wherein the third logic circuitry is arranged to encode the reference signature data in accordance with a same error detection coding scheme as employed by the first logic circuitry.
9. A circuit as claimed in claim 1 , wherein the first logic circuitry is arranged to encode the actual signature data in accordance with a bit parity error detection scheme.
10. A circuit as claimed in claim 1 , wherein the second logic circuitry is triggered by a change to the received actual signature data.
11. A circuit as claimed in claim 1 , further comprising:
a monitoring unit operably coupled to the alert output; wherein
the monitoring unit is arranged to initiate an action in response to detection of the alert signal.
12. A circuit as claimed in claim 11 , wherein the action is a reprogramming of the register or issuance of a reset command.
13. A circuit as claimed in claim 1 , wherein the storage unit comprises reset logic circuitry arranged to set the storage unit to store a predetermined reset value in response to receipt of a reset command, the predetermined reset value is dependent upon a reset state of the register.
14. A circuit as claimed in claim 1 , wherein the storage unit is arranged to be updated with updated reference signature data in response to detection of a write access to the register.
15. A circuit as claimed in claim 14 , wherein the write access is detected by the first logic circuitry, the first logic circuitry being arranged to update the content of the storage unit with updated reference signature data in response to the detection of the write access.
16. A circuit as claimed in claim 1 , wherein the register comprises a volatile bit, and the first logic circuitry is arranged to exclude the value of the volatile bit when generating the actual signature data.
17. A circuit as claimed in claim 16 , wherein the first logic circuitry is arranged to exclude the value of the volatile bit by temporally suspending calculating the actual signature data.
18. A method of detecting a data integrity error in respect of a register in an integrated circuit coupled to a write bus, the method comprising:
encoding a reference collective state of the register as reference signature data and storing the reference signature data;
generating actual signature data encoding the actual collective state of the register;
comparing the actual signature data with the reference signature data stored by the storage unit;
generating an alert signal in response to the comparison identifying a difference between the actual signature data and the reference signature data, thereby ensuring detection of a data integrity error in respect of the register; and
selectively inhibiting onward propagation of the alert signal in response to a control input signal for inhibiting use of the alert signal.