IP Library Granted Patent US 9,466,708
Granted Patent B2
US 9,466,708 · App. 13/831,883 · Granted Oct 11, 2016

Method of forming a transistor and structure therefor

Inventors: Balaji Padmanabhan (Tempe, AZ); Prasad Venkatraman (Gilbert, AZ); Gordon M. Grivna (Mesa, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L29/7813H01L29/407H01L29/4175H01L29/41766H01L29/4236H01L29/66621H01L29/66636H01L29/66734H01L29/7834H01L29/7835H01L29/513
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Quick Facts
Patent No.
US 9,466,708
App. No.
13/831,883
Granted
Oct 11, 2016
Kind
B2
Abstract

In one embodiment, a semiconductor device is formed to include a gate structure extending into a semiconductor material that is underlying a first region of semiconductor material. The gate structure includes a conductor and also a gate insulator that has a first portion positioned between the gate conductor and a first portion of the semiconductor material that underlies the gate conductor. The first portion of the semiconductor material is configured to form a channel region of the transistor which underlies the gate conductor. The gate structure may also include a shield conductor overlying the gate conductor and having a shield insulator between the shield conductor and the gate conductor. The shield insulator may also have a second portion positioned between the shield conductor and a second portion of the gate insulator and a third portion overlying the shield conductor.

Claims (42)

1. A transistor comprising:

a semiconductor substrate of a first conductivity type, the semiconductor substrate having a first surface and a second surface;

a first semiconductor region having a second conductivity type on the first surface of the semiconductor substrate;

a second semiconductor region formed within the first semiconductor region wherein a portion of the first semiconductor region underlies the second semiconductor region, the second semiconductor region having the first conductivity type;

a gate structure formed in an opening that extends from the second semiconductor region into the first semiconductor region;

a gate conductor of the gate structure formed within the opening and overlying a first portion of the first semiconductor region;

a source region adjacent the gate conductor and spaced laterally from the gate conductor;

a gate insulator between the gate conductor and the first portion of the first semiconductor region and between the source region and the gate conductor wherein a channel region of the transistor is in the first portion of the first semiconductor region so that current flows laterally between the source region and under the gate structure;

a shield conductor overlying the gate conductor; and

a shield insulator between the gate conductor and the shield conductor.

2. The transistor of claim 1 wherein the gate structure is devoid of the shield conductor underlying the gate conductor.

3. The transistor of claim 1 further including a source contact conductor extending through the second semiconductor region and through the source region and into the first semiconductor region to form an ohmic electrical connection to the source region and the first semiconductor region.

4. The transistor of claim 3 further including an insulator positioned between a portion of the source contact conductor that extends through the second semiconductor region.

5. The transistor of claim 3 wherein the source contact conductor directly contacts the source region and forms the ohmic electrical connection thereto and wherein the source region is devoid of a separate doped contact region positioned between the source contact conductor and the source region.

6. The transistor of claim 3 wherein the source contact conductor directly contacts the first semiconductor region and forms the ohmic electrical connection thereto and wherein the first semiconductor region is devoid of a separate doped contact region positioned between the source contact conductor and the first semiconductor region.

7. The transistor of claim 3 wherein the source contact conductor also forms an ohmic electrical contact to the shield conductor.

8. The transistor of claim 1 wherein the shield insulator is tapered to have a thickness that decreases as a distance into the second semiconductor region increases.

9. The transistor of claim 1 wherein the shield conductor is formed within another opening that is formed to extend into the shield insulator.

10. A semiconductor device comprising:

a semiconductor material of a first conductivity type having a first surface and a second surface;

a first doped region within the semiconductor material and having a second conductivity type;

a gate structure extending into the semiconductor material that is underlying the first doped region;

a gate conductor of the gate structure;

a gate insulator of the gate structure extending through the first doped region into the semiconductor material and having a first portion of the gate insulator positioned between the gate conductor and a first portion of the semiconductor material that is external to the first doped region and that underlies the gate conductor wherein the first portion of the semiconductor material is a channel region of the semiconductor device wherein the channel region is configured so that current flows laterally under the gate structure;

a shield conductor of the gate structure overlying the gate conductor; and

a shield insulator having a first portion overlying the shield conductor.

11. The semiconductor device of claim 10 wherein the gate structure includes an opening extending from a surface of the first doped region into the semiconductor material with the gate insulator positioned on a bottom of the opening and the gate conductor within the opening and on the gate insulator.

12. The semiconductor device of claim 11 wherein a second portion of the gate insulator is positioned along a sidewall of the opening and abutting the shield insulator.

13. The semiconductor device of claim 11 wherein the shield conductor is within the opening and overlying the gate conductor.

14. The semiconductor device of claim 10 further including a source region of the semiconductor device adjacent to and spaced apart from the gate conductor wherein the source region is also adjacent to an interface of the semiconductor material and the first doped region.

15. The semiconductor device of claim 10 wherein the shield insulator also includes a second portion positioned between the shield conductor and the gate conductor, and a third portion positioned between the shield conductor and a second portion of the gate insulator.

16. The semiconductor device of claim 10 wherein the gate structure has an end positioned in the semiconductor material and wherein the shield conductor overlies the end of the gate structure.

17. The semiconductor device of claim 10 wherein the gate structure has an end in the semiconductor material and wherein at least a portion of the channel region underlies the end of the gate structure.

18. The semiconductor device of claim 10 having a source region formed along an interface of the first doped region and the semiconductor material.

19. A semiconductor device comprising:

a semiconductor material of a first conductivity type having a first surface and a second surface;

a first doped region of within the semiconductor material and having a second conductivity type;

a gate structure extending into the semiconductor material that is underlying the first region;

a gate conductor of the gate structure;

a gate insulator of the gate structure having a first portion of the gate insulator positioned between the gate conductor and a first portion of the semiconductor material that is external to the first doped region and that underlies the gate conductor wherein the first portion of the semiconductor material is a channel region of the semiconductor device;

a shield conductor of the gate structure overlying the gate conductor; and

a shield insulator having a first portion overlying the shield conductor and electrically insulating the shield conductor from the gate conductor.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 22, 2013
From: PADMANABHAN, BALAJI; VENKATRAMAN, PRASAD; GRIVNA, GORDON M.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 030070/0914 →
Continuity (1)
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