IP Library Granted Patent US 9,475,145
Granted Patent B2
US 9,475,145 · App. 13/826,362 · Granted Oct 25, 2016

Solder bump joint in a device including lamellar structures

Inventors: Su-Chun Yang (Hsinchu, TW); Chung-Jung Wu (Tainan, TW); Hsiao-Yun Chen (Hsinchu, TW); Yi-Li Hsiao (Hsinchu, TW); Chih-Hang Tung (Hsinchu, TW); Da-Yuan Shih (Hsinchu, TW); Chen-Hua Yu (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
B23K1/0016H01L23/49811H01L24/16H01L24/81H01L24/13H01L2224/1132H01L2224/1134H01L2224/1145H01L2224/11334H01L2224/11462H01L2224/131H01L2224/13014H01L2224/13111H01L2224/13139H01L2224/13147H01L2224/16057H01L2224/16058H01L2224/16145H01L2224/16225H01L2224/16227H01L2224/16506H01L2224/16507H01L2224/8193H01L2224/81121H01L2224/81191H01L2224/81815H01L2924/01322
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Quick Facts
Patent No.
US 9,475,145
App. No.
13/826,362
Granted
Oct 25, 2016
Kind
B2
Abstract

A method includes heating a solder bump above a melting temperature of the solder bump. The solder bump is stretched to increase a height of the solder bump. The solder bump is cooled down to form a solder bump joint in an electrical device.

Claims (28)

1. A device having a solder bump joint between a substrate having pads and a top die, comprising:

solder bumps, the solder bumps positioned between the pads on the substrate having pads and the top die, the solder bumps forming the solder bump joint and joining together the substrate having pads and the top die, the solder bumps comprising lamellar structures and having a contact angle of less than 90°, wherein at least one of the lamellar structures comprises a Sn-rich phase greater than 90% Sn, and the solder bumps are predominantly a eutectic Sn—Bi compound, and the eutectic Sn—Bi compound is free of Ag.

2. The device of claim 1 , wherein the lamellar structures are predominantly parallel to an axis of stretching.

3. The device of claim 1 , wherein a ratio of an average center width spacing to an average top contact width spacing is between 0.5 and 1.0.

4. The device of claim 1 , wherein the at least one lamellar structure includes an intermetallic compound (IMC) phase where the IMC phase is selected from at least one of: Cu 6 Sn 5 , Ni 3 Sn 4 or AuSn 4 .

5. The device of claim 1 , wherein said tin is part of an alloy of at least one of Sn—Cu, Sn—Zn, or Sn—Bi.

6. A package comprising:

a substrate having a top surface and a bottom surface;

a die having a top surface and a bottom surface, wherein the bottom surface of the die faces the top surface of the substrate; and

a solder bump electrically connected to the top surface of the substrate, wherein the solder bump is electrically connected to the bottom surface of the die, the solder bump having a center portion distal from the die and the substrate having a first average width, the solder bump having an edge portion proximate to the die or the substrate having a second average width less than the first average width, and a contact angle between the bottom surface of the die and an outer edge of the solder bump is less than 90°, and the solder bump comprises a first set of lamellar structures including a Bi-rich phase free of Ag, and a second set of lamellar structures has a different composition from the first set of lamellar structures.

7. The package of claim 6 , wherein the second set of lamellar structures includes a Sn-rich phase.

8. The package of claim 6 , wherein the first set of lamellar structures or the second set of lamellar structures extends parallel to the bottom surface of die.

9. The package of claim 8 , wherein the first set of lamellar structures or the second set of lamellar structures extends orthogonal to the bottom surface of die.

10. The package of claim 6 , wherein the first set of lamellar structures or the second set of lamellar structures extends orthogonal to the bottom surface of die.

11. The package of claim 6 , wherein the substrate comprises pads on the top surface of the substrate, and the pads comprise at least one of copper, silver, electroless nickel immersion gold, or electroless nickel electroless palladium immersion gold.

12. The package of claim 6 , wherein the solder bump has a crystal angle between a normal of the top surface of the substrate and a short crystal axis of the solder bump greater than 50°.

13. A package comprising:

a substrate having a top surface;

a pad on the top surface of the substrate;

a die having a bonding surface, wherein the bonding surface of the die faces the top surface of the substrate; and

a solder bump electrically connected to the pad, wherein the solder bump is electrically connected to the bonding surface of the die, the solder bump has a crystal angle between a normal of the top surface of the substrate and a short crystal axis of the solder bump greater than 50°, a contact angle between the bottom surface of the die and an outer edge of the solder bump is less than 90°, the solder bump comprises a plurality of sets of lamellar structures, and a first set of lamellar structures of the plurality of lamellar structures has a first composition, a second set of lamellar structures of the plurality of lamellar structures has a second composition different from the first composition, and the first composition and the second composition are free of Ag.

14. The package of claim 13 , wherein a set of lamellar structures of the plurality of lamellar structures is oriented parallel to the top surface of the substrate, and another set of lamellar structures of the plurality of lamellar structures is oriented perpendicular to the top surface of the substrate.

15. The package of claim 13 , wherein the first composition is a Sn-rich composition.

16. The package of claim 15 , wherein the Sn-rich composition includes greater than 90% Sn.

17. The package of claim 15 , wherein the second composition is a Bi-rich composition.

18. The package of claim 15 , wherein the first composition includes a Sn—Pb alloy.

19. The package of claim 15 , wherein at least one set of lamellar structures of the plurality of sets of lamellar structures includes an intermetallic compound (IMC) phase selected from at least one of: Cu 6 Sn 5 , Ni 3 Sn 4 or AuSn 4 .

20. The package of claim 15 , wherein at least one set of lamellar structures of the plurality of sets of lamellar structures includes an alloy of at least one of Sn—Cu, Sn—Zn, or Sn—Bi.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 26, 2013
From: YANG, SU-CHUN; WU, CHUNG-JUNG; CHEN, HSIAO-YUN; HSIAO, YI-LI; TUNG, CHIH-HANG; SHIH, DA-YUAN; YU, CHEN-HUA
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 030082/0198 →
Continuity (2)
Continuation In Part 13406198 · Feb 27, 2012
Related Publication 20130221521A1 · Aug 29, 2013