IP Library › Granted Patent US 9,484,273
Granted Patent B2
US 9,484,273 · App. 13/425,677 · Granted Nov 1, 2016

Apparatus for measuring impurities on wafer and method of measuring impurities on wafer

Inventor: Seung Wook Lee (Gyeongbuk, KR)
Assignee: LG SILTRON INC.
H01L22/12H01L21/67H01L21/6708H01L21/67051G01N1/32G01N1/4044G01N35/0099G01N2001/383
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Quick Facts
Patent No.
US 9,484,273
App. No.
13/425,677
Granted
Nov 1, 2016
Kind
B2
Abstract

Provided are an apparatus for measuring impurities on a wafer and a method of measuring impurities on a wafer. The apparatus includes: a wafer aligning device for aligning a wafer; a loading robot for moving and loading the aligned wafer; a rotation stage for rotating the loaded wafer; a scan robot for holding a natural oxide layer etching solution for the wafer and a metallic impurity recovery solution; and a container for receiving a predetermined etching solution and a recovery solution, wherein the scan robot removes an oxide layer on an edge region of the wafer.

Claims (9)

1. An apparatus for measuring impurities on a wafer, comprising:

a wafer aligning device for aligning a wafer;

a loading robot for moving and loading the aligned wafer;

a rotation stage for rotating the loaded wafer;

a scan robot for holding a natural oxide layer etching solution for the wafer and a metallic impurity recovery solution; and

a container for receiving a predetermined etching solution and a recovery solution, wherein the scan robot includes a tube disposed at the bottom end of the scan robot and holding the etching solution and the recovery solution, and the bottom of the tube has a diagonally-cut shape.

2. The apparatus according to claim 1 , wherein the tube holds the etching solution to remove an oxide layer on an edge region of the wafer, and a cut region in a bottom end of the tube is disposed on a lateral side of the wafer edge region.

3. The apparatus according to claim 2 , wherein the tube holds the recovery solution to collect metallic impurities on a surface of the wafer edge region having the oxide layer removed, and the cut region in the bottom end of the tube is disposed on the lateral side of the wafer edge region.

4. The apparatus according to claim 1 , wherein a cut region in a bottom end of the tube is disposed at a lateral side of the wafer edge region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 5, 2012
From: LEE, SEUNG WOOK
To: LG SILTRON INC.
Reel/Frame 028503/0213 →
Priority Claims (1)
KR 10-2011-0024738 · Mar 21, 2011 · national
Continuity (1)
Related Publication 20120260750A1 · Oct 18, 2012