IP Library Granted Patent US 9,496,396
Granted Patent B1
US 9,496,396 · App. 14/961,902 · Granted Nov 15, 2016

Semiconductor device and method for fabricating the same

Inventors: Yu-Ming Hsu (Changhua County, TW); Chun-Liang Kuo (Kaohsiung, TW); Tsang-Hsuan Wang (Kaohsiung, TW); Sheng-Hsu Liu (Changhua County, TW); Chieh-Lung Wu (Kaohsiung, TW); Chung-Min Tsai (Tainan, TW); Yi-Wei Chen (Taichung, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/7848H01L29/0847H01L29/24H01L29/66636
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Quick Facts
Patent No.
US 9,496,396
App. No.
14/961,902
Granted
Nov 15, 2016
Kind
B1
Abstract

A method for fabricating semiconductor device is disclosed. The method includes the steps of: (a) providing a substrate; (b) forming a gate structure on the substrate; (c) performing a first deposition process to form a first epitaxial layer adjacent to the gate structure and performing a first etching process to remove part of the first epitaxial layer at the same time; and (d) performing a second etching process to remove part of the first epitaxial layer.

Claims (19)

1. A method for fabricating semiconductor device, comprising:

(a) providing a substrate;

(b) forming a gate structure on the substrate;

(c) performing a first deposition process to form a first epitaxial layer adjacent to the gate structure and performing a first etching process to remove part of the first epitaxial layer at the same time; and

(d) performing a second etching process to remove part of the first epitaxial layer.

2. The method of claim 1 , further comprising repeating steps (c) and (d).

3. The method of claim 1 , further comprising forming dislocations on the first epitaxial layer in step (c).

4. The method of claim 3 , further comprising performing the second etching process to remove the dislocations.

5. The method of claim 1 , further comprising flowing silane-containing gas during the first deposition process.

6. The method of claim 1 , further comprising flowing chlorine-containing gas during the first etching process.

7. The method of claim 1 , further comprising flowing chlorine-containing gas during the second etching process.

8. The method of claim 1 , further comprising:

(e) performing a second deposition process to form a second epitaxial layer adjacent to the gate structure and performing a third etching process to remove part of the second epitaxial layer at the same time; and

(f) performing a fourth etching process to remove part of the second epitaxial layer.

9. The method of claim 8 , further comprising forming dislocations on the second epitaxial layer in step (e).

10. The method of claim 9 , further comprising performing the fourth etching process to remove the dislocations.

11. The method of claim 8 , wherein the duration of step (c) is greater than the duration of step (e).

12. The method of claim 8 , wherein the duration of step (d) is greater than the duration of step (f).

13. The method of claim 8 , wherein the first epitaxial layer and the second epitaxial layer comprise SiP.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2025
From: UNITED MICROELECTRONICS CORP.
To: STELLAR SEMICONDUCTOR JAPAN GK
Reel/Frame 071913/0125 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 8, 2015
From: HSU, YU-MING; KUO, CHUN-LIANG; WANG, TSANG-HSUAN; LIU, SHENG-HSU; WU, CHIEH-LUNG; TSAI, CHUNG-MIN; CHEN, YI-WEI
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 037229/0427 →
Priority Claims (1)
TW 104136928 A · Nov 10, 2015 · national