IP Library Granted Patent US 9,502,267
Granted Patent B1
US 9,502,267 · App. 14/316,190 · Granted Nov 22, 2016

Integrated circuit packaging system with support structure and method of manufacture thereof

Inventors: HeeJo Chi (Yeoju-gun, KR); Bartholomew Liao Chung Foh (Singapore, SG); Sheila Marie L. Alvarez (Singapore, SG); Zigmund Ramirez Camacho (Singapore, SG); Dao Nguyen Phu Cuong (Singapore, SG)
Assignee: STATS ChipPAC Pte. Ltd.
H01L21/4857H01L21/568H01L23/5383
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Quick Facts
Patent No.
US 9,502,267
App. No.
14/316,190
Granted
Nov 22, 2016
Kind
B1
Abstract

An integrated circuit packaging system, and a method of manufacture thereof, includes: a support structure having: an internal insulation layer having a hole, a device connection side, and a removal mark characteristic of a conductive seed layer removed at the device connection side, a first conductive pad in the hole at the device connection side, and an exterior insulation layer over the first conductive pad at the device connection side; an integrated circuit over the exterior insulation layer; and an encapsulation over the integrated circuit.

Claims (54)

1. A method of manufacture of an integrated circuit packaging system comprising:

forming a support structure including:

providing a carrier having a conductive seed layer,

forming an interior insulation layer directly on the conductive seed layer,

forming an internal insulation layer directly on the interior insulation layer and the conductive seed layer,

etching the conductive seed layer at a device connection side of the internal insulation layer,

forming a hole of the internal insulation layer with the interior insulation layer removed at the device connection side,

forming a first conductive pad in the hole at the device connection side,

forming a second conductive pad having an internal surface directly on a system connection side of the internal insulation layer, the system connection side opposite to the device connection side,

forming an exterior insulation layer over the first conductive pad and directly on the device connection side, and

forming a second exterior insulation layer over and partially directly on a second pad external surface of the second conductive pad, the second exterior insulation layer directly on the system connection side, and the second pad external surface facing away from the internal surface, and

wherein the internal insulation layer is within the support structure;

mounting an integrated circuit over the exterior insulation layer at the device connection side; and

forming an encapsulation over the integrated circuit.

2. The method as claimed in claim 1 wherein forming the support structure includes forming the support structure having a conductive trace in another hole of the internal insulation layer at the device connection side with a conductive paste.

3. The method as claimed in claim 1 wherein forming the support structure includes forming the support structure having a via and the second conductive pad, the via within the internal insulation layer, at the system connection side of the internal insulation layer, and directly on the first conductive pad, and the second conductive pad directly on the via and the system connection side.

4. The method as claimed in claim 1 wherein forming the support structure includes forming the support structure having a conductive plate directly on a pad external surface of the first conductive pad.

5. The method as claimed in claim 1 wherein forming the support structure includes forming the support structure having a via below the hole and in the internal insulation layer with the first conductive pad directly on the via.

6. A method of manufacture of an integrated circuit packaging system comprising:

forming a support structure including:

providing a carrier having a conductive seed layer,

forming an interior insulation layer directly on the conductive seed layer,

forming an internal insulation layer directly on the interior insulation layer and the conductive seed layer,

etching the conductive seed layer at a device connection side of the internal insulation layer,

forming a hole of the internal insulation layer with the interior insulation layer removed at the device connection side,

forming a first conductive pad in the hole at the device connection side,

forming a second conductive pad having an internal surface directly on a system connection side of the internal insulation layer, the system connection side opposite to the device connection side,

forming an exterior insulation layer over the first conductive pad, directly on the device connection side, and partially exposing the first conductive pad and the internal insulation layer, and

forming a second exterior insulation layer over and partially directly on a second pad external surface of the second conductive pad, the second exterior insulation layer directly on the system connection side, and the second pad external surface facing away from the internal surface, and

wherein the internal insulation layer is within the support structure;

mounting an integrated circuit over the exterior insulation layer at the device connection side; and

forming an encapsulation over the integrated circuit.

7. The method as claimed in claim 6 wherein forming the support structure includes forming the support structure having a conductive trace in another hole of the internal insulation layer at the device connection side and the first conductive pad in the hole at the device connection side with conductive pastes.

8. The method as claimed in claim 6 wherein forming the support structure includes forming the support structure having a via, the second conductive pad, and the second exterior insulation layer, wherein the via is within the internal insulation layer, at the system connection side of the internal insulation layer, and is directly on the first conductive pad, and the second conductive pad is directly on the via and the system connection side, and the second exterior insulation layer is partially directly on the second conductive pad.

9. The method as claimed in claim 6 wherein forming the support structure includes forming the support structure having a conductive trace in the internal insulation layer and a conductive plate directly on a pad external surface of the first conductive pad and a trace external surface of the conductive trace.

10. The method as claimed in claim 6 wherein forming the support structure includes forming the support structure having a via below the hole and in the internal insulation layer with the first conductive pad directly on the via and having a pad external surface below the device connection side.

11. An integrated circuit packaging system comprising:

a support structure having:

an internal insulation layer having a hole, a device connection side, and a system connection side opposite to the device connection side, the internal insulation layer within the support structure,

a first conductive pad in the hole at the device connection side,

a second conductive pad having an internal surface directly on the system connection side,

an exterior insulation layer over the first conductive pad and directly on the device connection side, and

a second exterior insulation layer over and partially directly on a second pad external surface of the second conductive pad, the second exterior insulation layer directly on the system connection side, and the second pad external surface facing away from the internal surface;

an integrated circuit over the exterior insulation layer; and

an encapsulation over the integrated circuit.

12. The system as claimed in claim 11 wherein the support structure includes a conductive trace in another hole of the internal insulation layer at the device connection side, the conductive trace formed with a conductive paste.

13. The system as claimed in claim 11 wherein the support structure includes a via and the second conductive pad, the via within the internal insulation layer, at the system connection side of the internal insulation layer, and directly on the first conductive pad, and the second conductive pad directly on the via and the system connection side.

14. The system as claimed in claim 11 wherein the support structure includes a conductive plate directly on a pad external surface of the first conductive pad.

15. The system as claimed in claim 11 wherein the support structure includes a via below the hole and in the internal insulation layer with the first conductive pad directly on the via.

16. The system as claimed in claim 11 wherein the support structure includes the exterior insulation layer partially exposing the first conductive pad and the internal insulation layer.

17. The system as claimed in claim 16 wherein the support structure includes a conductive trace in another hole of the internal insulation layer at the device connection side and the first conductive pad in the hole at the device connection side, the conductive trace and the first conductive pad formed with conductive pastes.

18. The system as claimed in claim 16 wherein the support structure includes a via, the second conductive pad, and the second exterior insulation layer, wherein the via is within the internal insulation layer, at the system connection side of the internal insulation layer, and is directly on the first conductive pad, the second conductive pad is directly on the via and the system connection side, and the second exterior insulation layer is partially directly on the second conductive pad.

19. The system as claimed in claim 16 wherein the support structure includes a conductive trace in the internal insulation layer and a conductive plate directly on a pad external surface of the first conductive pad and a trace external surface of the conductive trace.

20. The system as claimed in claim 16 wherein the support structure includes a via below the hole and in the internal insulation layer with the first conductive pad directly on the via and having a pad external surface below the device connection side.

Assignments (2)
CHANGE OF NAME Recorded Jul 22, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 039439/0430 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2014
From: CHI, HEEJO; FOH, BARTHOLOMEW LIAO CHUNG; ALVAREZ, SHEILA MARIE L.; CAMACHO, ZIGMUND RAMIREZ; CUONG, DAO NGUYEN PHU
To: STATS CHIPPAC LTD.
Reel/Frame 033623/0466 →