Techniques for providing a semiconductor memory device
Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region.
1. A memory cell comprising:
a first region coupled to a source line;
a second region coupled to a bit line;
a body region capacitively coupled to at least one word line and disposed between the first region and the second region; and
a third region coupled to a carrier injection line;
wherein the first region, the second region, and the body region have a common first doping polarity.
2. The memory cell of claim 1 , wherein the third region has a second doping polarity that is different from the first doping polarity.
3. The memory cell of claim 1 , wherein the first region is coupled to a first poly plug and the second region is coupled to a second poly plug.
4. The memory cell of claim 1 , wherein the first region, the second region, the body region, and the third region are arranged in a contiguous horizontal configuration on a substrate.
5. The memory cell of claim 4 , wherein the first region, the second region, and the body region are doped with donor impurities.
6. The memory cell of claim 5 , wherein the third region is doped with acceptor impurities.
7. The memory cell of claim 4 , wherein the first region, the second region, and the body region are doped with acceptor impurities.
8. The memory cell of claim 7 , wherein the third region is doped with donor impurities.
9. The memory cell of claim 4 , wherein the first region, the second region, and the body region are undoped regions.
10. The memory cell of claim 4 , wherein the body region is coupled to a first doped region and the third region is coupled to a second doped region.
11. The memory cell of claim 10 , wherein the second doped region is doped with acceptor impurities having a concentration higher than the doped third region.
12. The memory cell of claim 1 , wherein the first region, the second region, and the body region are arranged in a contiguous vertical configuration on a substrate.
13. The memory cell of claim 12 , wherein the first region, the second region, and the body region are doped with donor impurities.
14. The memory cell of claim 13 , wherein the third region is doped with acceptor impurities.
15. The memory cell of claim 14 , wherein the third region is made of a P-well region.
16. The memory cell of claim 12 , wherein the first region, the second region, and the body region are doped with acceptor impurities.
17. The memory cell of claim 16 , wherein the third region is doped with donor impurities.
18. The memory cell of claim 17 , wherein the third region is made of an N-well region.
19. The memory cell of claim 12 , wherein the source line and the bit line are arranged on opposite sides of the memory cell.
20. The memory cell of claim 1 , wherein the first region, the second region, and the body region have different doping concentrations.