Semiconductor memory device including a repeater circuit on main data lines

1. A semiconductor device comprising:

first and second memory cell arrays, each of first and second memory cell arrays including a plurality of memory cells;

a first main data line arranged above the first memory cell array to transfer data read from the first memory cell array;

a second main data line arranged above the second memory cell array to transfer data read from the second memory cell array;

a main amplifier coupled to the second main data line to amplify the data on the second main data line; and

a repeater circuit coupled to the first and second main data lines, the repeater circuit further comprising:

a read repeater circuit configured to transfer data on the first main data line to the second main data line;

a write repeater circuit configured to transfer data from the second main data line to the first main data line; and

an equalizing circuit configured to precharge the first main data line.

2. The semiconductor device as claimed in claim 1 , wherein the repeater circuit is arranged between the first and second memory cell arrays.

3. The semiconductor device as claimed in claim 1 , wherein the repeater circuit includes a read repeater circuit to drive the second main data line responsive to the data on the first main data line, and a write repeater circuit to drive the first main data line responsive to the data on the second main data line.

4. The semiconductor device as claimed in claim 3 , further comprising a control circuit to activate the main amplifier after activating the read repeater circuit responsive to a read command, and to activate the write repeater circuit after activating the main amplifier responsive to a write command.

5. The semiconductor device as claimed in claim 1 , wherein a data read operation is performed on one of the first and second memory cell arrays while a data read operation the other of the first and second memory cell arrays is being out of service.

6. The semiconductor device as claimed in claim 5 , wherein the first memory cell array includes a first local data line that may be coupled to the first main data line, and the second memory cell array includes a second local data line that may be coupled to the second main data line.

7. The semiconductor device as claimed in claim 6 , wherein the first memory cell array includes a plurality of first bit lines, a selected one of first bit lines coupled to the first local data line, and the second memory cell array includes a plurality of second bit lines, a selected one of the second bit lines coupled to the second local data line.

8. The semiconductor device as claimed in claim 7 , wherein the first memory cell array includes a plurality of first column switches, a selected one of the first column switches being turned ON to couple the selected one of the first bit lines to the first local data line, and the second memory cell array includes a plurality of second column switches, a selected one of the second column switches being turned ON to couple the selected one of the second bit lines to the second local data line.

9. A semiconductor device comprising:

a first memory bank and a second memory bank, each of the first and second memory banks including:

first and second memory cell arrays,

a plurality of first main data lines associated with the first memory cell array,

a plurality of second main data lines associated with the second memory cell array,

a plurality of main amplifiers, each of the plurality of main amplifiers coupled to an associated one of the plurality of second main data lines, and

a plurality of repeater circuits each coupled to an associated one of the plurality of first main data lines and to an associated one of the plurality of second main data lines, each repeater circuit of the plurality of repeater circuits further comprising:

a read repeater circuit configured to transfer data on the associated one of the plurality of first main data lines to an associated one of the plurality of main amplifiers via the associated one of the second main data lines;

a write repeater circuit configured to transfer data from the associated one of the second main data lines to the associated one of the first main data lines;

an equalizing circuit configured to precharge the associated one of the first main data lines; and

a plurality of data buses each coupled to an associated one of the plurality of main amplifiers of the first memory bank and further coupled to an associated one of the plurality of main amplifiers of the second memory bank.

10. The semiconductor device as claimed in claim 9 , wherein each of the plurality of data buses includes a first bus coupled to an associated one of the plurality of main amplifiers of the first memory bank and a second bus coupled to an associated one of the plurality of main amplifiers of the second memory bank, and the semiconductor device further comprises a plurality of data repeater circuits each coupled to the first and second buses of an associated one of the plurality of data buses.

11. The semiconductor device as claimed in claim 9 , wherein the first memory cell array includes a plurality of first local data lines to transfer data read from the first memory cell array to the plurality of first main data lines, and the second memory cell array includes a plurality of second local data lines to transfer data read from the second memory cell array to the plurality of second main data lines.

12. The semiconductor device as claimed in claim 11 , wherein the first memory cell array includes a plurality of first sense amplifiers and includes a plurality of first bit lines each coupled to an associated one or ones of memory cells therein and to an associated one of the plurality of first sense amplifiers, and the second memory cell array includes a plurality of second sense amplifiers and includes a plurality of second bit lines each coupled to an associated one or ones of memory cells therein and to an associated one of the plurality of second sense amplifiers.

13. The semiconductor device as claimed in claim 12 , wherein the first memory cell array includes a plurality of first switches each coupled to an associated one of the plurality of first sense amplifiers and to an associated one of the plurality of first local data lines, and the second memory cell array includes a plurality of second switches each coupled to an associated one of the plurality of second sense amplifiers and to an associated one of the plurality of second local data lines.

14. The semiconductor device as claimed in claim 13 , further comprising a plurality of first select lines each coupled to an associated one of the plurality of first switches, a plurality of second select lines each coupled to an associated one of the plurality of second switches, and a plurality of switch repeaters coupled to an associated one of the plurality of first select lines and to an associated one of the plurality of second select lines to transfer a select signal to the associated one of the plurality of first select lines from the associated one of the plurality of second select lines.

15. A semiconductor memory device comprising:

a first memory cell array;

a second memory cell array;

a plurality of first main IO lines associated with the first memory cell array;

a plurality of second main IO lines provided for the second memory cell array;

wherein the first memory cell array includes

a memory mat including a plurality of memory cells each coupled to an associated one of a plurality of bit lines and to an associated one of a plurality of sub word lines,

a sub word driver circuit coupled to the plurality of sub word lines; and

a plurality of sense amplifier circuits each coupled to an associated one of the plurality of bit lines and to an associated one of the plurality of first main IO lines to amplify data on the associated one of the plurality of bit lines and transfer the amplified data to the associated one of the plurality of first main IO lines responsive to a plurality of control signals,

wherein the second memory cell array includes

a memory mat including a plurality of memory cells each coupled to an associated one of a plurality of bit lines and to an associated one of a plurality of sub word lines,

a sub word driver circuit coupled to the plurality of sub word lines; and

a plurality of sense amplifier circuits each coupled to an associated one of the plurality of bit lines and to an associated one of the plurality of second main IO lines to amplify data on the associated one of the plurality of bit lines and transfer the amplified data to the associated one of the plurality of second main IO lines responsive to the plurality of control signals,

a plurality of first control lines each coupled to an associated one of the plurality of sense amplifier circuits of the first memory cell array;

a plurality of second control lines each couple to an associated one of the plurality of sense amplifier circuits of the second memory cell array; and

a plurality of repeater circuits coupled to an associated one of the plurality of first main IO lines and to an associated one of the second main IO lines, each of the plurality of repeater circuits further comprising:

a read repeater circuit configured to transfer data on the associated one of the plurality of first main IO lines to the associated one of the second main IO lines;

a write repeater circuit configured to transfer data from the associated one of the plurality of second main IO lines to the associated one of the first main IO lines; and

an equalizing circuit configured to precharge the associated one of the plurality of first main IO lines.

16. The device as claimed in claim 15 , further comprising

a plurality of main IO repeater circuits each coupled to an associated one of the plurality of first main IO lines and to an associated one of the plurality of second main IO lines.

17. The device as claimed in claim 15 , further comprising

a plurality of main amplifiers each coupled to an associated one of the plurality of first main IO lines.

18. The device as claimed in claim 15 , further comprising

a decoder circuit coupled to the plurality of first lines to supply the plurality of control signals respectively to the plurality of first lines.

19. The device as claimed in claim 15 , wherein the plurality of first main IO lines and the plurality of first lines are arranged in parallel and the plurality of second main IO lines and the plurality of second lines are arranged in parallel.

20. The device as claimed in claim 15 , wherein each of the plurality of sense amplifier circuits in the first and second memory cell arrays includes a plurality of switch transistors each coupled an associated one of the plurality of main IO lines therein and including a control terminal to receive an associated one of the plurality of control signals.