Power semiconductor device having trench gate type IGBT and diode regions
Switching loss is reduced. A first surface of a semiconductor substrate has a portion included in an IGBT region and a portion included in a diode region. Trenches formed in the first surface include a gate trench and a boundary trench disposed between the gate trench and the diode region. A fourth layer of the semiconductor substrate is provided on the first surface and has a portion included in the diode region. The fourth layer includes a trench-covering well region that covers the deepest part of the boundary trench, a plurality of isolated well regions, and a diffusion region that connects the trench-covering well region and the isolated well regions. The diffusion region has a lower impurity concentration than that of the isolated well regions. A first electrode is in contact with the isolated well regions and away from the diffusion region.
1. A power semiconductor device having a trench gate type IGBT region and a diode region for reverse conduction of said IGBT region, the power semiconductor device comprising:
a semiconductor substrate having a first surface and a second surface opposite said first surface, said first surface having a portion included in said IGBT region and a portion included in said diode region, said semiconductor substrate including,
a first layer of a first conductivity type that is provided on said first surface and away from said second surface in said IGBT region,
a second layer of a second conductivity type that is provided on said first surface and away from said second surface in said IGBT region, said second conductivity type being different from said first conductivity type,
a third layer of said second conductivity type that is provided away from said first surface and said second surface in said IGBT region and in contact with said first layer and said second layer,
a fourth layer of said second conductivity type that has a portion included in said diode region and is provided on said first surface and away from said second surface,
a fifth layer of said first conductivity type that is in contact with said third layer in said IGBT region and is in contact with said fourth layer in said diode region,
a sixth layer of said second conductivity type that is provided on said second surface, is at least partially included in said IGBT region, and is in contact with said fifth layer, and
a seventh layer of said first conductivity type that is provided on said second surface, is at least partially included in said diode region, and is in contact with said fifth layer,
said first surface of said semiconductor substrate being provided with a plurality of trenches each having a side wall, said plurality of trenches including a gate trench and a boundary trench, said gate trench having a gate side wall that has a surface formed of said first layer, said third layer, and said fifth layer as said side wall, and said boundary trench being disposed between said gate trench and said diode region and having a boundary side wall that faces said diode region;
a gate insulating film that covers said side walls of said trenches;
a trench electrode provided in said trenches via said gate insulating film;
an interlayer insulating film provided on said first surface of said semiconductor substrate and having an IGBT opening and a diode opening, said IGBT opening exposing said first layer and said second layer, and said diode opening exposing part of said fourth layer;
a first electrode that is provided on said interlayer insulating film, is in contact with said first layer and said second layer through said IGBT opening, and is in contact with said fourth layer through said diode opening; and
a second electrode that is provided on said second surface of said semiconductor substrate and is in contact with said sixth layer and said seventh layer,
wherein said fourth layer includes a trench-covering well region that covers a deepest part of said boundary side wall, a plurality of isolated well regions that are disposed separately from said trench-covering well region, and a diffusion region that connects said trench-covering well region and said plurality of isolated well regions, said diffusion region having a lower impurity concentration than impurity concentrations of said trench-covering well region and said isolated well regions when impurity concentrations in a direction parallel to said first surface of said semiconductor substrate are compared, and
wherein said first electrode is in contact with said isolated well regions and away from said diffusion region.
2. The power semiconductor device according to claim 1 , wherein
said first electrode is in contact with only said isolated well regions of said fourth layer.
3. The power semiconductor device according to claim 1 , wherein
said sixth layer has a portion that extends from said IGBT region into said diode region.