IP Library Granted Patent US 9,558,979
Granted Patent B2
US 9,558,979 · App. 14/046,469 · Granted Jan 31, 2017

Method for manufacturing semiconductor device

Inventors: Hwa Seob Choi (Incheon, KR); Yu Sung Jang (Yongin-si, KR); Tai Young Eum (Suwon-si, KR); Jee Ho Lee (Suwon-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H01L21/681H01L21/6835H01L21/6836H01L21/67092H01L2221/6834H01L2221/68327Y10T279/11Y10T279/21
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Quick Facts
Patent No.
US 9,558,979
App. No.
14/046,469
Granted
Jan 31, 2017
Kind
B2
Abstract

A wafer chuck holds a wafer on a surface thereof such that an image of the wafer can be formed from light reflected by the surface of the wafer chuck. The surface of the wafer chuck is a planar surface that has a reflectivity equal to or greater than 40%, and/or a whiteness index value equal to or greater than 90. The wafer chuck can include a ceramic containing aluminum oxide having a purity equal to or greater than 95%. The planar surface of the wafer chuck is such that light illuminating the surface of the wafer chuck is reflected by the surface of the wafer chuck through the wafer. The wafer chuck can be used with an apparatus for cutting the wafer, and the light reflected by the surface can be used to form an image of the wafer used identifying cutting lines on the wafer.

Claims (44)

1. An apparatus for cutting a wafer comprising:

a wafer chuck configured to hold the wafer on a surface thereof, wherein the surface of the wafer chuck on which the wafer is held has a reflectivity equal to or greater than 40%;

a light source configured to illuminate the surface of the wafer chuck through the wafer;

an image capture device configured to form an image of the wafer based on light emitted by the light source and reflected by the surface of the wafer chuck;

a processor configured to determine locations of cutting lines on the wafer based on the formed image; and

a cutting assembly configured to cut the wafer along the cutting lines determined by the processor;

wherein electrode patterns of a plurality of semiconductor devices disposed on a surface of the wafer impede passage of the reflected light through the wafer, and the image capture device forms the image of the wafer showing first regions of the wafer in which light emitted by the light source is reflected by the surface of the wafer chuck to the image capture device, and second regions of the wafer having electrode patterns therein in which light emitted by the light source is not reflected by the surface of the wafer chuck to the image capture device.

2. The apparatus of claim 1 , wherein the surface of the wafer chuck on which the wafer is held has a whiteness index value equal to or greater than 90.

3. The apparatus of claim 2 , wherein the wafer chuck is made of a ceramic containing aluminum oxide having a purity equal to or greater than 95%.

4. The apparatus of claim 1 , wherein the wafer is a transparent wafer.

5. The apparatus of claim 1 , wherein the wafer chuck is a porous ceramic, and the wafer is held to the surface of the porous wafer chuck using vacuum adsorption through pores of the ceramic wafer chuck.

6. The apparatus of claim 1 , further comprising an adhesive layer disposed on the surface of the wafer chuck to hold the wafer on the surface of the wafer chuck and formed of a transparent material.

7. The apparatus of claim 1 , wherein electrode patterns of a plurality of semiconductor devices disposed on a surface of the wafer impede passage of the reflected light through the wafer, and the image capture device forms the image of the wafer showing first regions of the wafer in which light emitted by the light source is reflected by the surface of the wafer chuck to the image capture device, and second regions of the wafer having electrode patterns therein in which fight emitted by the light source is not reflected by the surface of the wafer chuck to the image capture device.

8. The apparatus of claim 1 , wherein the processor determines locations of cutting lines on the wafer by performing steps of:

identifying at least one location in the formed image matching a pre-set image of an electrode pattern of a plurality of electrode patterns disposed on the wafer; and

determining locations of the cutting lines on the wafer based on the identified at least one location and on a location of a cutting line in the matched pre-set image of the electrode pattern.

9. The apparatus of claim 1 , wherein the processor is configured to determine locations of a first set of cutting lines on the wafer based on the formed image prior to cutting of the wafer by the cutting assembly, and is further configured to determine locations of a second set of cutting lines on the wafer based on another formed image of the wafer following the cutting of the wafer along the first set of cutting lines.

10. An apparatus for cutting a wafer comprising:

a wafer chuck configured to hold the wafer on a surface thereof, wherein the surface of the wafer chuck on which the wafer is held has a whiteness index value equal to or greater than 90;

a light source configured to illuminate the surface of the wafer chuck through the wafer;

an image capture device configured to form an image of the wafer cased on light emitted by the light source that is passed through the wafer and reflected by a portion of the surface of the wafer chuck that is covered by the wafer;

a processor configured to determine locations of cutting lines on the wafer based on the formed image; and

a cutting assembly configured to cut the wafer along the cutting lines determined by the processor;

wherein electrode patterns of a plurality of semiconductor devices disposed on a surface of the wafer impede passage of the reflected light through the wafer, and the image capture device forms the image of the wafer showing first regions of the wafer in which light emitted by the light source is reflected by the surface of the wafer chuck to the image capture device, and second regions of the wafer having electrode patterns therein in which light emitted by the light source is not reflected by the surface of the wafer chuck to the image capture device.

11. The apparatus of claim 10 , wherein the wafer chuck is made of a ceramic containing aluminum oxide having a purity equal to or greater than 95%.

12. The apparatus of claim 11 , wherein the surface of the wafer chuck on which the wafer is held has a reflectivity equal to or greater than 40%.

13. The apparatus of claim 10 , wherein electrode patterns of a plurality of semiconductor devices disposed on a surface of the wafer impede passage of the reflected light through the wafer, and the image capture device forms the image of the wafer showing first regions of the wafer in which light emitted by the light source is reflected by the surface of the wafer chuck to the image capture device, and second regions of the wafer having electrode patterns therein in which light emitted by the light source is not reflected by the surface of the wafer chuck to the image capture device.

14. The apparatus of claim 10 , wherein the processor determines locations of cutting lines on the wafer by performing steps of:

identifying at least one location in the formed image matching a pre-set image of an electrode pattern of a plurality of electrode patterns disposed on the wafer; and

determining locations of the cutting lines on the wafer based on the identified at least one location and on a location of a cutting line in the matched pre-set image of the electrode pattern.

15. The apparatus of claim 10 , wherein the processor is configured to determine locations of a first set of cutting lines on the wafer based on the formed image prior to cutting of the wafer by the cutting assembly, and is further configured to determine locations of a second set of cutting lines on the wafer based on another formed image of the wafer following the cutting of the wafer along the first set of cutting lines.

16. An apparatus for cutting a wafer comprising:

a wafer chuck configured to hold the wafer on a surface thereof, wherein the wafer chuck is made of a ceramic containing aluminum oxide having a purity equal to or greater than 95%;

a light source configured to illuminate the surface of the wafer chuck through the wafer;

an image capture device configured to form an image of the wafer based on light emitted by the light source and reflected by the surface of the wafer chuck;

a processor configured to determine locations of cutting lines on the wafer based on the formed image; and

a cutting assembly configured to cut the wafer along the cutting lines determined by the processor,

wherein electrode patterns of a plurality of semiconductor devices disposed on a surface of the wafer impede passage of the reflected light through the wafer, and the image capture device forms the image of the wafer showing first regions of the wafer in which light emitted by the light source is reflected by the surface of the wafer chuck to the image capture device, and second regions of the wafer having electrode patterns therein in which light emitted by the light source is not reflected by the surface of the wafer chuck to the image capture device.

17. The apparatus of claim 16 , wherein the surface of the wafer chuck on which the wafer is held has a reflectivity equal to or greater than 40%.

18. The apparatus of claim 17 , wherein the surface of the wafer chuck on which the wafer is held has a whiteness index value equal to or greater than 90.

19. The apparatus of claim 16 , wherein the processor determines locations of cutting lines on the wafer by performing steps of:

identifying at least one location in the formed image matching a pre-set image of an electrode pattern of a plurality of electrode patterns disposed on the wafer; and

determining locations of the cutting lines on the wafer based on the identified at least one location and on a location of a cutting line in the matched pre-set image of the electrode pattern.

20. The apparatus of claim 16 , wherein the processor is configured to determine locations of a first set of cutting lines on the wafer based on the formed image prior to cutting of the wafer by the cutting assembly, and is further configured to determine locations of a second set of cutting lines on the wafer based on another formed image of the wafer following the cutting of the wafer along the first set of cutting lines.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 4, 2013
From: CHOI, HWA SEOB; JANG, YU SUNG; EUM, TAI YOUNG; LEE, JEE HO
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 031350/0373 →
Priority Claims (1)
KR 10-2013-0047577 · Apr 29, 2013 · national
Continuity (1)
Related Publication 20140319784A1 · Oct 30, 2014