IP Library Granted Patent US 9,559,174
Granted Patent B2
US 9,559,174 · App. 15/068,708 · Granted Jan 31, 2017

Semiconductor film, transistor, semiconductor device, display device, and electronic appliance

Inventors: Akihisa Shimomura (Kanagawa, JP); Yasumasa Yamane (Kanagawa, JP); Yuhei Sato (Kanagawa, JP); Takahisa Ishiyama (Kanagawa, JP); Kenichi Okazaki (Tochigi, JP); Chiho Kawanabe (Tochigi, JP); Masashi Oota (Kanagawa, JP); Noritaka Ishihara (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/24C01G15/006H01L29/045H01L29/7869C01P2002/72C01P2002/89C01P2004/04C01P2006/40
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,559,174
App. No.
15/068,708
Granted
Jan 31, 2017
Kind
B2
Abstract

Favorable electrical characteristics are given to a semiconductor device. Furthermore, a semiconductor device having high reliability is provided. One embodiment of the present invention is an oxide semiconductor film having a plurality of electron diffraction patterns which are observed in such a manner that a surface where the oxide semiconductor film is formed is irradiated with an electron beam having a probe diameter whose half-width is 1 nm. The plurality of electron diffraction patterns include 50 or more electron diffraction patterns which are observed in different areas, the sum of the percentage of first electron diffraction patterns and the percentage of second electron diffraction patterns accounts for 100%, the first electron diffraction patterns account for 90% or more, the first electron diffraction pattern includes observed points which indicates that a c-axis is oriented in a direction substantially perpendicular to the surface where the oxide semiconductor film is formed.

Claims (53)

1. A semiconductor device comprising:

an oxide semiconductor layer comprising In, Ga, and Zn; and

an insulating layer that contains oxygen in excess of the stoichiometric composition,

wherein the insulating layer and the oxide semiconductor layer overlap each other,

wherein an atomic ratio of In to Ga and Zn in the oxide semiconductor layer satisfies In:Ga:Zn=x:y:z,

wherein, in an equilibrium diagram with vertices of the three elements of In, Ga, and Zn, the atomic ratio is within a range of an area surrounded by line segments that connect first coordinates (x:y:z=35:20:22), second coordinates (x:y:z=7:4:11), third coordinates (x:y:z=5:1:6), fourth coordinates (x:y:z=25:10:14), and the first coordinates, in this order, and

wherein the oxide semiconductor layer includes a plurality of crystals.

2. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer includes a nanocrystal.

3. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer includes a plurality of c-axis aligned crystals.

4. A transistor comprising the semiconductor device according to claim 1 , wherein the oxide semiconductor layer includes a channel region.

5. The semiconductor device according to claim 1 , further comprising:

a second oxide layer; and

a third oxide layer,

wherein the oxide semiconductor layer is in contact with a top surface of the second oxide layer, and

wherein the third oxide layer is in contact with a top surface of the oxide semiconductor layer.

6. The semiconductor device according to claim 5 , wherein the third oxide layer is in contact with a side surface of the second oxide layer, and a side surface and the top surface of the oxide semiconductor layer.

7. The semiconductor device according to claim 5 , wherein electron affinity of oxide included in the oxide semiconductor layer is larger than electron affinity of oxide included in the second oxide layer and electron affinity of oxide included in the third oxide layer.

8. A semiconductor device comprising:

an oxide semiconductor layer comprising In, an element M, and Zn, and

an insulating layer that contains oxygen in excess of the stoichiometric composition,

wherein the insulating layer and the oxide semiconductor layer overlap each other,

wherein the element M is at least one of aluminum, gallium, yttrium, and tin,

wherein an atomic ratio of In to the element M and Zn in the oxide semiconductor layer satisfies In:M:Zn=x:y:z,

wherein, in an equilibrium diagram with vertices of the three elements of In, the element M, and Zn, the atomic ratio is within a range of an area surrounded by line segments that connect first coordinates (x:y:z=35:20:22), second coordinates (x:y:z=7:4:11), third coordinates (x:y:z=5:1:6), fourth coordinates (x:y:z=25:10:14), and the first coordinates, in this order, and

wherein the oxide semiconductor layer includes a plurality of crystals.

9. The semiconductor device according to claim 8 , wherein the oxide semiconductor layer includes a nanocrystal.

10. The semiconductor device according to claim 9 , wherein the oxide semiconductor layer includes a plurality of c-axis aligned crystals.

11. A transistor comprising the semiconductor device according to claim 8 , wherein the oxide semiconductor layer includes a channel region.

12. The semiconductor device according to claim 8 , further comprising:

a second oxide layer; and

a third oxide layer,

wherein the oxide semiconductor layer is in contact with a top surface of the second oxide layer, and

wherein the third oxide layer is in contact with a top surface of the oxide semiconductor layer.

13. The semiconductor device according to claim 12 , wherein the third oxide layer is in contact with a side surface of the second oxide layer, and a side surface and the top surface of the oxide semiconductor layer.

14. The semiconductor device according to claim 12 , wherein electron affinity of oxide included in the oxide semiconductor layer is larger than electron affinity of oxide included in the second oxide layer and electron affinity of oxide included in the third oxide layer.

15. An semiconductor device comprising:

an oxide semiconductor layer comprising In, Ga, and Zn; and

an insulating layer that contains oxygen in excess of the stoichiometric composition,

wherein the insulating layer and the oxide semiconductor layer overlap each other,

wherein an atomic ratio of In to Ga and Zn in the oxide semiconductor layer satisfies In:Ga:Zn=x:y:z,

wherein, in an equilibrium diagram with vertices of the three elements of In, Ga, and Zn, the atomic ratio is within a range of an area surrounded by line segments that connect first coordinates (x:y:z=35:20:22), second coordinates (x:y:z=7:4:11), third coordinates (x:y:z=5:1:6), fourth coordinates (x:y:z=25:10:14), and the first coordinates, in this order,

wherein the oxide semiconductor layer includes a plurality of crystals, and

wherein In:Ga=2:1.

16. The semiconductor device according to claim 15 , wherein the oxide semiconductor layer includes a nanocrystal.

17. The semiconductor device according to claim 15 , wherein the oxide semiconductor layer includes a plurality of c-axis aligned crystals.

18. A transistor comprising the semiconductor device according to claim 15 , wherein the oxide semiconductor layer includes a channel region.

19. The semiconductor device according to claim 15 , further comprising:

a second oxide layer; and

a third oxide layer,

wherein the oxide semiconductor layer is in contact with a top surface of the second oxide layer, and

wherein the third oxide layer is in contact with a top surface of the oxide semiconductor layer.

20. The semiconductor device according to claim 19 , wherein the third oxide layer is in contact with a side surface of the second oxide layer, and a side surface and the top surface of the oxide semiconductor layer.

21. The semiconductor device according to claim 19 , wherein electron affinity of oxide included in the oxide semiconductor layer is larger than electron affinity of oxide included in the second oxide layer and electron affinity of oxide included in the third oxide layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 12, 2016
From: SHIMOMURA, AKIHISA; YAMANE, YASUMASA; SATO, YUHEI; ISHIYAMA, TAKAHISA; OKAZAKI, KENICHI; KAWANABE, CHIHO; OOTA, MASASHI; ISHIHARA, NORITAKA
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 038572/0899 →
Priority Claims (5)
JP 2014-032192 · Feb 21, 2014 · national
JP 2014-098071 · May 9, 2014 · national
JP 2014-122792 · Jun 13, 2014 · national
JP 2014-131834 · Jun 26, 2014 · national
JP 2014-218310 · Oct 27, 2014 · national
Continuity (2)
Continuation 14626049 · Feb 19, 2015
Related Publication 20160197193A1 · Jul 7, 2016