Reduced trench profile for a gate
The present disclosure is directed to a gate structure for a transistor. The gate structure is formed on a substrate and includes a trench. There are sidewalls that line the trench. The sidewalls have a first dimension at a lower end of the trench and a second dimension at an upper end of the trench. The first dimension being larger than the second dimension, such that the sidewalls are tapered from a lower region to an upper region. A high k dielectric liner is formed on the sidewalls and a conductive liner is formed on the high k dielectric liner. A conductive material is in the trench and is adjacent to the conductive liner. The conductive material has a first dimension at the lower end of the trench that is smaller than a second dimension at the upper end of the trench.
1. A device, comprising:
a substrate;
a transistor structure formed on the substrate, the transistor including:
a doped layer on the substrate;
source-drain regions in the doped layer;
a trench through the doped layer and between the source-drain regions;
a first sidewall in the trench;
a second sidewall in the trench on the first sidewall, the second sidewall including:
a first portion having a first width;
a second portion having a second width, the second width being smaller than the first width; and
a curved portion between the first portion and the second portion, the curved portion having a third width that transitions from the first width to the second width, the first portion, the second portion, and the curved portion being aligned along a first direction, the curved portion and the source-drain regions being aligned along a second direction that is substantially perpendicular to the first direction;
a first liner; and
a conductive material that is separated from the second sidewall by the first liner.
2. The device of claim 1 wherein the transistor structure includes a second liner between the first liner and the conductive material.
3. The device of claim 1 wherein the trench has a lower portion and an upper portion, the second sidewall having the first width adjacent to the lower portion of the trench and the second width adjacent to the upper portion of the trench.
4. The device of claim 1 wherein the transistor structure includes a self-aligned cap on the conductive material.
5. The device of claim 1 wherein the first sidewall is an oxide and the second sidewall is a silicon nitride.
6. The device of claim 1 wherein the first liner is formed on the substrate between portions of the first sidewall and a second liner is formed on the first liner.
7. The device of claim 6 wherein the second liner is a titanium based liner.
8. A device, comprising:
a substrate;
a doped layer on top of the substrate;
source-drain regions in the doped layer;
a gate structure, including:
a trench in the doped layer;
sidewalls that line the trench, the sidewalls including:
a first portion at a first end of the trench, the first portion having a first planar surface and a second planar surface opposite to the first planar surface, the first portion having a first distance between the first planar surface and the second planar surface;
a second portion at a second end of the trench, the second portion having a third planar surface and a fourth planar surface opposite to the third planar surface, the second portion having a second distance between the third planar surface and the fourth planar surface, the first distance being larger than the second distance; and
a third portion between the first portion and the second portion, the third portion having a fifth planar surface and a curved surface opposite to the fifth planar surface, the third portion being closer to the first end than to the second end of the trench;
a first liner that is adjacent to the sidewalls; and
a conductive material in the trench that is adjacent to the first liner, the conductive material having a first dimension at the first end of the trench and a second dimension at the second end of the trench.
9. The device of claim 8 wherein the first dimension of the conductive material is smaller than the second dimension of the conductive material.
10. The device of claim 8 wherein the gate structure includes a second liner between the sidewalls and the first liner.
11. A device, comprising:
a substrate;
a doped layer on top of the substrate;
source and drain regions formed in the doped layer;
a first dielectric layer on the doped layer;
a fin having a first portion extending from the substrate through the doped layer and a second portion extending at least partially into the first dielectric layer;
a trench through the first dielectric layer and the doped layer;
a gate structure in the trench, the gate structure overlapping the fin, the gate structure including:
a sidewall having a first thickness closer to the substrate and lateral to the first portion of the fin, and a second thickness closer and lateral to the second portion of the fin, the first thickness being greater than the second thickness.
12. The device of claim 11 wherein the gate structure includes a first liner on the sidewall.
13. The device of claim 12 wherein a first liner abuts a top surface of the substrate.
14. The device of claim 12 wherein the gate structure includes a second liner on the first liner.
15. The device of claim 11 wherein the gate structure includes a conductive plug between the sidewalls.
16. A device, comprising:
a substrate;
a doped layer on the substrate, the doped layer including source-drain regions;
a first dielectric layer on the doped layer;
a trench through the doped layer and the first dielectric layer;
a gate structure in the trench, the gate structure including conductive material, the conductive material including:
a first portion having a first thickness;
a second portion having a second thickness that is greater than the first thickness; and
a curved portion between the first portion and the second portion, the curved portion having a third thickness that transitions from the first thickness to the second thickness, the first portion and the curved portion being lateral to the doped layer, the second portion being lateral to the first dielectric layer.
17. The device of claim 16 , wherein the gate structure further includes a sidewall having a third portion and a fourth portion, the third portion having a fourth thickness, the fourth portion having a fifth thickness that is less than the fourth thickness, the third portion being lateral to the first portion of the conductive material, the fourth portion being lateral to the second portion of the conductive material.
18. The device of claim 16 , further comprising a cap overlying the gate structure, the cap being in the trench.
19. The device of claim 16 , further comprising a second dielectric layer between the substrate and the doped layer.
20. The device of claim 16 , wherein the gate structure further includes:
a sidewall; and
a conformal liner formed in the trench, on a part of the substrate within the trench, and adjacent to the sidewall.