Methods and systems for clocking a physical layer interface

Inventors: Prasad Chalasani (San Jose, CA); Venkata N. S. N. Rao (Fremont, CA)

Assignee: SOCTRONICS, INC.

H03L7/00 G06F1/04 G06F1/06 G06F1/08 G06F1/10 G06F1/12 G06F1/14 G06F1/28 G06F13/385 H03K19/0175 H03K19/017509 H03L7/0802 H03L7/093 H04L7/0012 H04L25/028 H04L25/0276 Y02B60/1228 Y02B60/1235

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Quick Facts

Patent No.: US 9,564,905
App. No.: 14/066,583
Granted: Feb 7, 2017
Kind: B2

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Abstract

A method for clocking a physical layer (“PHY”) and a controller of a computing device, comprises the steps of: generating a reference clock signal; synchronizing a plurality of clock signals as a function of the reference clock signal; and clocking the controller and the PHY using the plurality of synchronized clock signals.

Claims (21)

1. A method for clocking a physical layer (“PHY”) and a controller of a computing device, wherein the PHY has an address macro and a double data rate physical interface (“DFI”), comprising the steps of:

generating one or more reference clock signals;

synchronizing a plurality of clock signals as a function of the one or more reference clock signals, wherein the address macro is clocked by a first clock signal of the plurality of clock signals, wherein the first clock signal is synchronized to a certain one of the reference clock signals using a first clock generation and synchronization block, wherein the controller is clocked by a second clock signal of the plurality of clock signals, wherein the second clock signal is synchronized to the certain one of the reference clock signals using a second clock generation and synchronization block, wherein the DFI is clocked by a third clock signal of the plurality of clock signals, and wherein the third clock signal is synchronized to the certain one of the reference clock signals using a third clock generation and synchronization block; and

clocking the controller and the PHY using the plurality of synchronized clock signals.

2. The method of claim 1 wherein the first clock signal is distributed across the address macro and wherein the first clock signal is synchronized to the certain one of the reference clock signals using a feedback signal from the address macro.

3. The method of claim 2 wherein the feedback signal is a clock signal at an endpoint of the clock distribution for the address macro.

4. The method of claim 1 wherein the second clock signal is distributed across the controller, and wherein the second clock signal is synchronized to the certain one of the reference clock signals using a feedback signal from the controller.

5. The method of claim 4 wherein the feedback signal is a clock signal at an endpoint of the controller clock distribution.

6. The method of claim 1 wherein the third clock signal is distributed across the DFI, and wherein the third clock signal is synchronized to the certain one of the reference clock signals using a feedback signal from the DFI.

7. The method of claim 6 wherein the feedback signal is a clock signal at an endpoint of the DFI clock distribution.

8. A method for clocking a physical layer (“PHY”) and a controller of a computing device, wherein the PHY has an address macro and a double data rate physical interface (“DFI”), comprising the steps of:

generating one or more reference clock signals;

clocking the controller and the PHY using the plurality of synchronized clock signals.

9. The method of claim 8 wherein the first clock signal is distributed across the address macro, wherein the first clock signal is synchronized to the certain one of the reference clock signals using a feedback signal (“I_CLK_MEM”), and wherein the feedback signal is a clock signal at an endpoint of the clock distribution for the address macro.

10. The method of claim 8 wherein the second clock signal is distributed across the controller, wherein the second clock signal is synchronized to the certain one of the reference clock signals using a feedback signal (“I_CLK_CTL”), and wherein the feedback signal is a clock signal at an endpoint of the controller clock distribution.

11. The method of claim 8 wherein the third clock signal is distributed across the DFI, wherein the third clock signal is synchronized to the certain one of the reference clock signals using a feedback signal (“I_CLK_DFI”), and wherein the feedback signal is a clock signal at an endpoint of the DFI clock distribution.

12. A method for clocking a physical layer (“PHY”) and a controller of a computing device, wherein the PHY has an address macro and a double data rate physical interface (“DFI”), comprising the steps of:

generating one or more reference clock signals;

synchronizing a plurality of clock signals as a function of the one or more reference clock signals, wherein the address macro is clocked by a first clock signal (“O_CLK_MEM”) of the plurality of clock signals, wherein the first clock signal is synchronized to a certain one of the reference clock signals, wherein the controller is clocked by a second clock signal (“O_CLK_CTL”) of the plurality of clock signals, wherein the second clock signal is synchronized to a the certain one of the reference clock signals, wherein the DFI is clocked by a third clock signal (“O_CLK_DFI”) of the plurality of clock signals, wherein the third clock signal is synchronized to the certain one of the reference clock signals, wherein the first clock signal is distributed across the address macro, wherein the first clock signal is synchronized to the certain one of the reference clock signals using a first feedback signal (“I_CLK_MEM”), wherein the first feedback signal is a clock signal at an endpoint of the clock distribution for the address macro, wherein the second clock signal is distributed across the controller, wherein the second clock signal is synchronized to the certain one of the reference clock signals using a second feedback signal (“I_CLK_CTL”), wherein the second feedback signal is a clock signal at an endpoint of the controller clock distribution, wherein the third clock signal is distributed across the DFI, wherein the third clock signal is synchronized to the certain one of the reference clock signals using a third feedback signal (“I_CLK_DFI”), and wherein the third feedback signal is a clock signal at an endpoint of the DFI clock distribution; and

clocking the controller and the PHY using the plurality of synchronized clock signals.

Assignments (4)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 29, 2020

From: INVECAS, INC.

To: SYNOPSYS, INC.

Reel/Frame 051971/0624 →

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 20, 2019

From: SOCTRONICS, INC.

To: INVECAS, INC.

Reel/Frame 049233/0278 →

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 13, 2015

From: KOOL CHIP, INC.