Integrated circuit structure and method for reducing polymer layer delamination

1. An integrated circuit structure comprising:

a substrate;

a metal pad over the substrate;

a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad;

a first polymer layer over the PPI structure, the first polymer layer including an untreated portion and a treated portion, the treated portion having a higher hydrogen concentration than the untreated portion;

an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, wherein a sidewall of the UBM is aligned with a sidewall of the treated portion of the first polymer layer and wherein the UBM extends over the untreated portion and does not extend over the treated portion layer; and

the treated portion of the first polymer layer forming a barrier layer on a top surface of the untreated portion of the first polymer layer adjacent to the UBM, the barrier layer being nonconductive, wherein the barrier layer does not extend into the first portion of the top surface of the first polymer layer, a top surface of the treated portion of the first polymer layer being co-planar with a bottom surface of the UBM.

2. The integrated circuit structure of claim 1 , wherein the barrier layer has a thickness of about 1 nm to about 10 nm.

3. The integrated circuit structure of claim 1 , wherein the PPI structure comprises copper, and the UBM comprises copper.

4. The integrated circuit structure of claim 1 , wherein the first polymer layer is selected from a group consisting of polyimide (PI), polybenzoxazole (PBO), benzocyclobuten (BCB), epoxy, silicone, acrylates, nano-filled pheno resin, siloxane, fluorinated polymer, polynorbornene, and combinations thereof.

5. The integrated circuit structure of claim 1 , further comprising a bump on the UBM.

6. The integrated circuit structure of claim 1 , further comprising a second polymer layer underlying the first polymer layer, and wherein the PPI structure is formed in an opening of the second polymer layer and electrically connected to the metal pad.

7. An integrated circuit structure comprising:

a first die, a second die and a molding compound filling a space between the first die and the second die, wherein the first die comprises a metal pad;

a copper pillar in physical contact with the metal pad, the copper pillar comprises a first surface facing away from the metal pad;

a dielectric layer covering sidewalls of the copper pillar, the dielectric layer comprising a second surface facing away from the metal pad, the second surface extending from the copper pillar to a first edge of the first die, wherein the first surface, the second surface and a surface of the molding compound all lie in the same plane;

a post-passivation interconnect (PPI) structure overlying the first die and electrically connected to the metal pad;

a first polymer layer over the PPI structure, the first polymer layer including a surface region and a bulk region, the surface region having a higher hydrogen concentration relative to the bulk region;

a under bump metallurgy (UBM) formed in an opening in the first polymer layer and electrically connected the PPI structure; and

wherein the surface region of the first polymer layer forms a barrier layer on a top surface of the first polymer layer adjacent to the UBM, the barrier layer being nonconductive and extending in a direction towards the UBM no further than a sidewall of the UBM, the surface region of the first polymer layer being co-planar with a bottom surface of the UBM.

8. The integrated circuit structure of claim 7 , further comprising a second polymer layer over the first die, the second die and the molding compound, wherein the PPI structure is formed in an opening in the second polymer layer and electrically connected to the metal pad.

9. The integrated circuit structure of claim 7 , further comprising a bump on the UBM.

10. The integrated circuit structure of claim 7 , wherein the barrier layer has a thickness of about 1 nm to about 10 nm.

11. An integrated circuit structure comprising:

a substrate;

a metal pad over the substrate;

a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad;

a first polymer layer over the PPI structure, the first polymer layer having a top surface;

an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, wherein the UBM extends over a first portion of the top surface of the first polymer layer and does not extend over a second portion of the top surface of the first polymer layer; and

wherein the top surface of the first polymer layer comprises a nonconductive barrier layer in the second portion of the top surface of the first polymer layer which nonconductive barrier layer does not extend into the first portion of the top surface of the first polymer layer, wherein the barrier layer has a first boundary facing the substrate, the first portion has a second boundary facing away from the substrate, and the first boundary of the barrier layer is closer to the substrate than the second boundary of the first portion, and wherein the integrated circuit structure is part of a fan-out wafer level package, a top surface of the barrier layer of the polymer layer being co-planar with a bottom surface of the UBM.

12. The integrated circuit structure of claim 11 , wherein the nonconductive barrier layer extends into the first polymer layer to a depth of from about 1 nm to about 10 nm.

13. The integrated circuit structure of claim 11 , wherein the second portion of the top surface of the first polymer layer has a higher hydrogen concentration relative the first portion of the top surface of the first polymer layer.

14. The integrated circuit structure of claim 11 , further comprising a second substrate having a second post-passivation interconnect (PPI) structure over the second substrate and a molding compound interjacent the substrate and the second substrate and interjacent the PPI structure and the second PPI structures.

15. The integrated circuit structure of claim 11 , further comprising a second polymer layer underlying the first polymer layer, and wherein the PPI structure is formed in an opening of the second polymer layer and electrically connected to the metal pad.

16. The integrated circuit structure of claim 11 , further comprising:

another substrate;

another metal pad over the another substrate;

another post-passivation interconnect (PPI) structure over the another substrate and electronically connected to the another metal pad;

another first polymer layer over the another PPI structure, the another first polymer layer having another top surface;

another under bump metallurgy (UBM) extending into another opening in the another first polymer layer and electronically connected to the another PPI structure, wherein the another UBM extends over a first portion of the another top surface of the another first polymer layer and does not extend over a second portion of the another top surface of the another first polymer layer; and

wherein the another top surface of the another first polymer layer comprises another nonconductive barrier layer in the second portion of the another top surface of the another first polymer layer which another nonconductive barrier layer does not extend into the first portion of the another top surface of the another first polymer layer, the second portion of the another top surface of the another first polymer layer having a higher hydrogen concentration relative the first portion of the another top surface of the another first polymer layer.

17. The integrated circuit structure of claim 1 , wherein the treated portion has a constant thickness in a direction perpendicular to a major surface of the substrate.

18. The integrated circuit structure of claim 7 , wherein the barrier layer has a top surface that remains planar as the barrier layer extends from the UBM.

19. The integrated circuit structure of claim 11 , wherein the barrier layer and the first portion of the top surface of the first polymer layer share an interface perpendicular to a major surface of the substrate, the interface having a distance that is equal to a thickness of the barrier layer.

20. The integrated circuit structure of claim 7 , wherein the barrier layer has a first portion of the barrier layer and a second portion of the barrier layer, wherein the first portion of the barrier layer covers the molding compound and the second portion of the barrier layer covers the copper pillar.