Static random access memory
A static random access memory (SRAM) is disclosed. The SRAM includes a plurality of SRAM cells on a substrate, in which each of the SRAM cells comprises: a gate structure on the substrate; a first interlayer dielectric (ILD) layer around the gate structure; a first contact plug in the first ILD layer; a second ILD layer on the first ILD layer; and a second contact plug in the second ILD layer and electrically connected to the first contact plug.
1. A static random access memory (SRAM), comprising:
a plurality of SRAM cells on a substrate, wherein each of the SRAM cells comprises:
a gate structure on the substrate;
a first interlayer dielectric (ILD) layer around the gate structure;
a first contact plug in the first ILD layer;
a second ILD layer on the first ILD layer; and
a second contact plug in the second ILD layer and electrically connected to the first contact plug.
2. The SRAM of claim 1 , wherein each of the SRAM cells comprises two pull-up transistors, two pull-down transistors, and two access transistors.
3. The SRAM of claim 1 , further comprising a stop layer between the first ILD layer and the second ILD layer.
4. A static random access memory (SRAM), comprising:
a first SRAM cell on a substrate, comprising:
a first gate structure on the substrate;
a first interlayer dielectric (ILD) layer around the first gate structure;
a first contact plug in the first ILD layer;
a second ILD layer on the first ILD layer; and
a second contact plug in the second ILD layer and electrically connected to the first contact plug, wherein the second contact plug and the first contact plug comprise a misalignment therebetween.
5. The SRAM of claim 4 , wherein an edge of the second contact plug and the top surface of the first contact plug comprise a step profile therebetween.
6. The SRAM of claim 4 , further comprising at least one fin-shaped structure on the substrate.
7. The SRAM of claim 6 , wherein the first contact plug overlaps at least two edges of the fin-shaped structure and the second contact plug only partially overlaps the fin-shaped structure.
8. The SRAM of claim 4 , further comprising a stop layer between the first ILD layer and the second ILD layer.
9. The SRAM of claim 4 , wherein the first SRAM cell comprises two pull-up transistors, two pull-down transistors, and two access transistors, wherein one of the two pull-up transistors comprises:
the first gate structure on the substrate;
the first interlayer dielectric (ILD) layer around the first gate structure;
the first contact plug in the first ILD layer;
the second ILD layer on the first ILD layer; and
the second contact plug in the second ILD layer and electrically connected to the first contact plug, wherein the second contact plug and the first contact plug comprise a misalignment therebetween.
10. The SRAM of claim 4 , wherein the SRAM device comprises two pull-up transistors, two pull-down transistors, and two access transistors, wherein each of the two pull-up transistors comprises:
the first gate structure on the substrate;
the first ILD layer around the gate structure;
the first contact plug in the first ILD layer;
the second ILD layer on the first layer; and
the second contact plug in the second ILD layer and electrically connected to the first contact plug, wherein the second contact plug and the first contact plug comprise a misalignment therebetween.
11. The SRAM of claim 4 , further comprising a second SRAM cell electrically connected to the first SRAM cell, the second SRAM cell comprises:
a second gate structure on the substrate;
the first interlayer dielectric (ILD) layer around the second gate structure;
a third contact plug in the first ILD layer;
the second ILD layer on the first ILD layer; and
a fourth contact plug in the second ILD layer and electrically connected to the third contact plug, wherein the fourth contact plug and the third contact plug comprise a misalignment therebetween.
12. The SRAM of claim 11 , wherein an edge of the fourth contact plug and the top surface of the third contact plug comprise a step profile therebetween.
13. The SRAM of claim 11 , further comprising at least one fin-shaped structure on the substrate.
14. The SRAM of claim 13 , wherein the third contact plug overlaps at least two edges of the fin-shaped structure and the fourth contact plug only partially overlaps the fin-shaped structure.
15. The SRAM of claim 11 , further comprising a stop layer between the first ILD layer and the second ILD layer.
16. The SRAM of claim 11 , wherein the second SRAM cell comprises two pull-up transistors, two pull-down transistors, and two access transistors, wherein one of the two pull-up transistors comprises:
the second gate structure on the substrate;
the first interlayer dielectric (ILD) layer around the second gate structure;
the third contact plug in the first ILD layer;
the second ILD layer on the first ILD layer; and
the fourth contact plug in the second ILD layer and electrically connected to the third contact plug, wherein the fourth contact plug and the third contact plug comprise a misalignment therebetween.
17. The SRAM of claim 11 , wherein the second SRAM cell comprises two pull-up transistors, two pull-down transistors, and two access transistors, wherein each of the two pull-up transistors comprises:
the second gate structure on the substrate;
the first interlayer dielectric (ILD) layer around the second gate structure;
the third contact plug in the first ILD layer;
the second ILD layer on the first ILD layer; and
the fourth contact plug in the second ILD layer and electrically connected to the third contact plug, wherein the fourth contact plug and the third contact plug comprise a misalignment therebetween.