Method for fabricating bump structure without UBM undercut
A method for fabricating bump structure without UBM undercut uses an electroless Cu plating process to selectively form a Cu UBM layer on a Ti UBM layer within an opening of a photoresist layer. After stripping the photoresist layer, there is no need to perform a wet etching process on the Cu UBM layer, and thereby the UBM structure has a non-undercut profile.
1. A method of forming a semiconductor device, comprising:
providing a substrate;
forming a first under-bump metallurgy (UBM) layer on the substrate;
forming a mask layer on the first UBM layer, wherein the mask layer has an opening exposing a portion of the first UBM layer;
performing an electroless plating process to form a second UBM layer on the exposed portion of the first UBM layer within the opening of the mask layer, wherein performing the electroless plating comprises forming a layer of palladium over the first UBM layer and plating a copper layer over the layer of palladium;
forming a solder layer overlying the second UBM layer within the opening of the mask layer;
removing the mask layer;
removing the first UBM layer not covered by the solder layer; and
forming a Cu post between the second UBM layer and the solder layer within the opening of the mask layer, wherein the Cu post and the second UBM layer have sidewalls that are substantially coplanar to each other, and wherein an entirety of the solder layer and the Cu post have sidewalls that are substantially coplanar to each other.
2. The method of claim 1 , wherein the second UBM layer comprises a copper layer.
3. The method of claim 1 , wherein the electroless plating process comprises removing an oxide from the first UBM layer prior to forming the layer of palladium.
4. The method of claim 1 , further comprising forming a polymer layer between the first UBM layer and the substrate.
5. The method of claim 1 , further comprising forming a cap layer on the Cu post within the opening of the mask layer.
6. The method of claim 5 , wherein the cap layer comprises a nickel layer formed on the Cu post.
7. The method of claim 5 , wherein the cap layer comprises a nickel layer formed on the Cu post, and a gold layer formed on the nickel layer.
8. The method of claim 1 , wherein the first UBM layer comprises a titanium layer.
9. The semiconductor device of claim 1 , wherein the copper post has a thickness greater than 30 microns (μm).
10. A semiconductor device, comprising:
a semiconductor substrate;
a first under-bump metallurgy (UBM) layer having first sidewalls formed on the semiconductor substrate;
a second UBM layer having second sidewalls formed on the first UBM layer, wherein the first sidewalls and second sidewalls are substantially coplanar, and the second UBM layer comprises palladium;
a copper post formed on the second UBM layer;
a nickel layer formed on the copper post, the copper post separating the nickel layer from the second UBM layer; and
a solder layer formed on the nickel layer, wherein the copper post and the second UBM layer have sidewalls that are substantially coplanar to each other, and wherein an entirety of the solder layer and the copper post have sidewalls that are substantially coplanar to each other.
11. The semiconductor device of claim 10 , wherein the first UBM layer comprises a copper layer.
12. The semiconductor device of claim 10 , wherein the first UBM layer comprises a titanium layer.
13. The semiconductor device of claim 10 , wherein the second UBM layer has a non-undercut profile.
14. The semiconductor device of claim 10 , wherein the copper post has a thickness greater than 30 microns (μm).
15. The semiconductor device of claim 10 , further comprising a gold layer formed on the nickel layer.
16. A semiconductor device, comprising:
a semiconductor substrate;
a first under-bump metallurgy (UBM) layer having first sidewalls formed on the semiconductor substrate;
a second UBM layer having second sidewalls formed on the first UBM layer, wherein the first sidewalls and second sidewalls are substantially coplanar, and the second UBM layer comprises copper and palladium;
a copper post formed on the second UBM layer; and
a nickel layer formed on the copper post, the copper post separating the nickel layer from the second UBM layer,
wherein the second UBM layer is a palladium-containing copper alloy layer; and
a solder layer formed over the nickel layer, and wherein an entirety of the solder nickel layer and the Cu post have sidewalls that are substantially coplanar to each other.
17. The semiconductor device of claim 16 , wherein the copper post has a thickness greater than 30 microns (μm).
18. The semiconductor device of claim 16 , wherein the first under-bump metallurgy (UBM) layer comprises Ti, TiN, TaN, or Ta.
19. The semiconductor device of claim 16 , wherein the solder layer comprises Sn, SnAg, SnAgCu, SnAgZn, SnZn, Sn—In, Sn—Au, SnPb, SnCu, SnZnIn, SnAgSb, or Sn—Pb.
20. The semiconductor device of claim 16 , wherein the second UBM layer has a non-undercut profile.