Thin film transistor and display panel including the same
A thin film transistor is provided, which includes a gate electrode on a substrate; a channel layer overlapping the gate electrode; a dielectric layer between the gate electrode and the channel layer; a source electrode and a drain electrode electrically connecting to the channel layer; a passivation layer overlying the source electrode, the drain electrode, and the gate dielectric layer, wherein the channel layer includes two contact portions being in contact with the source electrode and the drain electrode, respectively, and a non-contact portion located between the two contact portions, and wherein one of the two contact portions has a first thickness in a first direction perpendicular to a surface of the substrate, and the non-contact portion has a second thickness less than the first thickness in the first direction.
1. A thin film transistor, comprising:
a gate electrode on a substrate;
a channel layer overlapping the gate electrode;
a gate dielectric layer disposed between the gate electrode and the channel layer;
a source electrode and a drain electrode electrically connected to the channel layer;
a passivation layer overlying the source electrode, the drain electrode, and the gate dielectric layer;
a via hole through the passivation layer; and
a conductive pattern on the passivation layer to serve as a pixel electrode, wherein the conductive pattern is in contact with the drain electrode through the via hole,
wherein the channel layer comprises an oxide semiconductor,
wherein the channel layer includes two contact portions being in contact with the source electrode and the drain electrode, respectively, and a non-contact portion located between the two contact portions, and
wherein one of the two contact portions has a first thickness in a first direction, the non-contact portion has a second thickness in the first direction, the first direction is perpendicular to a surface of the substrate, and the first thickness is greater than the second thickness.
2. The thin film transistor as claimed in claim 1 , further comprising an insulating capping layer covering the channel layer.
3. The thin film transistor as claimed in claim 2 , wherein a bottom surface of the insulating capping layer and a top surface of the channel layer have a substantially similar width.
4. The thin film transistor as claimed in claim 3 , wherein the bottom surface of the insulating capping layer and the top surface of the channel layer have a width difference of 0 μm to 2 μm.
5. The thin film transistor as claimed in claim 1 , wherein the source electrode and the drain electrode overlie two parts of the gate electrode.
6. The thin film transistor as claimed in claim 1 , wherein the material of the gate dielectric layer is selected from a group consisting of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, hafnium oxide, or combinations thereof.
7. The thin film transistor as claimed in claim 1 , wherein the material of the oxide semiconductor is selected from a group consisting of zinc oxide, indium oxide, indium gallium zinc oxide, tin oxide, or combinations thereof.
8. A display panel, comprising:
a substrate;
a thin film transistor on the substrate, comprising:
a gate electrode on the substrate;
a channel layer overlapping the gate electrode;
a gate dielectric layer disposed between the gate electrode and the channel layer;
a source electrode and a drain electrode electrically connected to the channel layer;
a passivation layer overlying the source electrode, the drain electrode, and the gate dielectric layer;
a via hole through the passivation layer; and
a conductive pattern on the passivation layer to serve as a pixel electrode, wherein the conductive pattern is in contact with the drain electrode through the via hole,
wherein the channel layer comprises an oxide semiconductor;
wherein the channel layer includes two contact portions being in contact with the source electrode and the drain electrode, respectively, and a non-contact portion located between the two contact portions, and
wherein one of the two contact portions has a first thickness in a first direction, the non-contact portion has a second thickness in the first direction, the first direction is perpendicular to a surface of the substrate, and the first thickness is greater than the second thickness.
9. The display panel as claimed in claim 8 further includes an insulating capping layer covering the channel layer.
10. The display panel as claimed in claim 9 , wherein a bottom surface of the insulating capping layer and a top surface of the channel layer have a substantially similar width.
11. The display panel as claimed in claim 10 , wherein the bottom surface of the insulating capping layer and the top surface of the channel layer have a width difference of 0 μm to 2 μm.
12. The display panel as claimed in claim 8 , wherein the source electrode and the drain electrode overlie two parts of the gate electrode.
13. The display panel as claimed in claim 8 , wherein the material of the gate dielectric layer is selected from a group consisting of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, hafnium oxide, or combinations thereof.
14. The display panel as claimed in claim 8 , wherein the material of the oxide semiconductor is selected from a group consisting of zinc oxide, indium oxide, indium gallium zinc oxide, tin oxide, or combinations thereof.