IP Library Granted Patent US 9,608,090
Granted Patent B2
US 9,608,090 · App. 15/170,904 · Granted Mar 28, 2017

Method for fabricating semiconductor device having fin structure that includes dummy fins

Inventor: En-Chiuan Liou (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/6681H01L21/28518H01L21/76895H01L21/823431H01L29/161H01L29/165H01L29/24H01L29/267H01L29/41791H01L29/66795H01L29/785H01L29/7845H01L29/7848H01L29/7853H01L29/7854H01L29/7856H01L2029/7858
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Quick Facts
Patent No.
US 9,608,090
App. No.
15/170,904
Granted
Mar 28, 2017
Kind
B2
Abstract

A method for fabricating semiconductor device is disclosed. First, a substrate, and a sacrificial mandrel is formed on the substrate, in which the sacrificial mandrel includes a first side and a second side with the indentation. Next, a spacer is formed adjacent to the first side and the second side of the sacrificial mandrel, the sacrificial mandrel is removed, and the spacer is used to remove part of the substrate for forming a fin-shaped structure and a dummy fin-shaped structure.

Claims (18)

1. A method for fabricating semiconductor device, comprising:

providing a substrate;

forming a sacrificial mandrel on the substrate, wherein the sacrificial mandrel comprises an indentation; and

forming a spacer adjacent to the sacrificial mandrel.

2. The method of claim 1 , wherein the sacrificial mandrel comprises a first side and a second side with the indentation, the method further comprises;

forming the spacer adjacent to the first side and the second side;

removing the sacrificial mandrel; and

using the spacer to remove part of the substrate for forming a fin-shaped structure and a dummy fin-shaped structure.

3. The method of claim 2 , wherein the dummy fin-shaped structure comprises a curve.

4. The method of claim 3 , wherein the curve is omega shaped.

5. The method of claim 2 further comprising:

performing a fin-cut process;

forming a gate structure on the fin-shaped structure;

forming a first epitaxial layer on the fin-shaped structure adjacent to two sides of the gate structure and a second epitaxial layer on the dummy fin-shaped structure; and

forming a contact plug on the first epitaxial layer and the second epitaxial layer.

6. The method of claim 5 , further comprising:

forming a silicide on the first epitaxial layer and the second epitaxial layer; and

forming the contact plug on the silicide.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 1, 2016
From: LIOU, EN-CHIUAN
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 038769/0245 →
Priority Claims (1)
TW 103142048 A · Dec 3, 2014 · national
Continuity (2)
Division 14588989 · Jan 5, 2015
Related Publication 20160276458A1 · Sep 22, 2016