TCAM field enable logic
A content addressable memory (“CAM”) field enabling logic comprises fields and field enable logics. The fields each have local match lines and a corresponding field enable control for enabling the respective field. The field enable logics are serially connected. Each of the fields is coupled to a corresponding one of the field enable logics via the respective local match lines. The corresponding field enable control for each of the fields is coupled to the corresponding one of the field enable logic and to any ones of the field enable logics that come after the corresponding one of the field enable logic along the serially-connected field enable logics.
1. A content addressable memory (“CAM”) field logic, comprising:
fields, wherein the fields each have local match lines and wherein the fields each have a corresponding field enable control for enabling the respective field; and
field enable logics for generating next global match lines,
wherein the field enable logics are serially connected,
wherein each of the fields is coupled to a corresponding one of the field enable logics via the respective local match lines, and
wherein the corresponding field enable control for each of the fields is coupled to the corresponding one of the field enable logic and to any ones of the field enable logics that come after the corresponding one of the field enable logic along the serially-connected field enable logics.
2. The CAM field enabling logic of claim 1 wherein the field enable logics each comprise a mask generation block for generating a global mask and a local mask and a next global match line generation block for generating the next global match lines.
3. The CAM field enabling logic of claim 2 wherein the next global match line generation block comprises a first OR gate, a second OR gate, and an AND gate, wherein the global mask and previous global match lines are coupled to inputs of the first OR gate, wherein the local match lines and the local mask are coupled to the inputs of the second OR gate, and wherein outputs of the first OR gate and the second OR gate are coupled to the inputs of the AND gate for generating the next global match lines.
4. The CAM field enabling logic of claim 3 wherein the previous global match lines are provided by a previous one of the field enable logics that is directly before the corresponding one of the field enable logic along the serially-connected field enable logics.
5. The CAM field enabling logic of claim 3 wherein the previous global match lines for a first one of the serially-connected field enable logics are coupled to a low logic value.
6. The CAM field enabling logic of claim 2 wherein the mask generation block comprises a first OR gate, a first NOR gate, and an inverter, wherein previous field enable controls are coupled to inputs of the first OR gate, wherein the local mask is generated by the output of the inverter, wherein the corresponding field enable control is coupled to an input of the inverter, and wherein the outputs of the first OR gate and the inverter are coupled to the inputs of the NOR gate to generate the global mask.
7. The CAM field enabling logic of claim 6 wherein the previous field enable controls for a first one of the serially-connected field enable logics is coupled to ground.
8. A method for content addressable memory (“CAM”) field enabling for a CAM having fields and serially-connected field enable logics, wherein the fields are each coupled to a corresponding one of the serially-connected field enable logics, comprising:
inputting a current field enable control and previous field enable controls to each of the serially-connected field enable logics;
generating a global mask and a local mask for each for each of the serially-connected field enable logics, wherein the local mask is generated as a function of the current field enable control, and wherein the global mask is generated as a function of the previous field enable controls and the local mask; and
providing global match lines from the serially-connected field enable logics based on the current field enable control, the previous field enable controls, the generated global mask, and the generated local mask for each of the serially-connected field enable logics.
9. The method of claim 8 wherein if the current field enable control for a select one of the field enable logics is unselected and the previous field enable controls for the select one of the field enable logics is unselected, then the corresponding field to the select one of the field enable logics is disabled, the global mask is set to evaluate any previous global match lines, and the local mask is set to prevent evaluating local match lines of the corresponding field.
10. The method of claim 8 wherein if the current field enable control for a select one of the field enable logics is selected and the previous field enable controls for the select one of the field enable logics is unselected, then the corresponding field to the select one of the field enable logics is active, the global mask is set to prevent evaluating any previous global match lines, and the local mask is set to evaluate local match lines of the corresponding field.
11. The method of claim 8 wherein if the current field enable control for a select one of the field enable logics is unselected and one or more of the previous field enable controls for the select one of the field enable logics is selected, then the corresponding field to the select one of the field enable logics is disabled, the global mask is set to evaluate any previous global match lines, and the local mask is set to prevent evaluating local match lines of the corresponding field.
12. The method of claim 8 wherein if the current field enable control for a select one of the field enable logics is selected and one or more of the previous field enable controls for the select one of the field enable logics is selected, then the corresponding field to the select one of the field enable logics is active, the global mask is set to evaluate any previous global match lines, and the local mask is set to evaluate local match lines of the corresponding field.
13. The method of claim 8 wherein for the first one of the serially-connected field enable logics the previous field enable controls are set to ground and inputs for the previous global match lines of the first one of the serially-connected field enable logics are set to ground.
14. The method of claim 8 wherein the field enable logics each comprise a mask generation block for generating a global mask and a local mask and a next global match line generation block for generating the next global match lines.
15. The method of claim 14 wherein the next global match line generation block comprises a first OR gate, a second OR gate, and an AND gate, wherein the global mask and previous global match lines are coupled to inputs of the first OR gate, wherein the local match lines and the local mask are coupled to the inputs of the second OR gate, and wherein outputs of the first OR gate and the second OR gate are coupled to the inputs of the AND gate for generating the next global match lines.
16. The method of claim 15 wherein the previous global match lines are provided by a previous one of the field enable logics that is directly before the corresponding one of the field enable logic along the serially-connected field enable logics.
17. The method of claim 15 wherein the previous global match lines for a first one of the serially-connected field enable logics are coupled to a low logic value.
18. The method of claim 14 wherein the mask generation block comprises a first OR gate, a first NOR gate, and an inverter, wherein previous field enable controls are coupled to inputs of the first OR gate, wherein the local mask is generated by the output of the inverter, wherein the corresponding field enable control is coupled to an input of the inverter, and wherein the outputs of the first OR gate and the inverter are coupled to the inputs of the NOR gate to generate the global mask.
19. The method of claim 18 wherein the previous field enable controls for a first one of the serially-connected field enable logics is coupled to ground.
20. A content addressable memory (“CAM”) field logic, comprising:
fields, wherein the fields each have local match lines and wherein the fields each have a corresponding field enable control for enabling the respective field; and
field enable logics for generating next global match lines,
wherein the field enable logics are serially connected,
wherein each of the fields is coupled to a corresponding one of the field enable logics via the respective local match lines,
wherein the corresponding field enable control for each of the fields is coupled to the corresponding one of the field enable logic and to any ones of the field enable logics that come after the corresponding one of the field enable logic along the serially-connected field enable logics,
wherein the field enable logics each comprise a mask generation block for generating a global mask and a local mask and a next global match line generation block for generating the next global match lines,
wherein the next global match line generation block comprises a first OR gate, a second OR gate, and an AND gate,
wherein the global mask and previous global match lines are coupled to inputs of the first OR gate,
wherein the local match lines and the local mask are coupled to the inputs of the second OR gate,
wherein outputs of the first OR gate and the second OR gate are coupled to the inputs of the AND gate for generating the next global match lines,
wherein the previous global match lines are provided by a previous one of the field enable logics that is directly before the corresponding one of the field enable logic along the serially-connected field enable logics,
wherein the previous global match lines for a first one of the serially-connected field enable logics are coupled to a low logic value,
wherein the mask generation block comprises a first OR gate, a first NOR gate, and an inverter,
wherein previous field enable controls are coupled to inputs of the first OR gate, wherein the local mask is generated by the output of the inverter,
wherein the corresponding field enable control is coupled to an input of the inverter, wherein the outputs of the first OR gate and the inverter are coupled to the inputs of the NOR gate to generate the global mask, and
wherein the previous field enable controls for a first one of the serially-connected field enable logics is coupled to ground.