IP Library Granted Patent US 9,647,072
Granted Patent B2
US 9,647,072 · App. 14/441,022 · Granted May 9, 2017

Silicon carbide semiconductor device

Inventors: Toru Hiyoshi (Osaka, JP); Takeyoshi Masuda (Osaka, JP); Keiji Wada (Osaka, JP); Takashi Tsuno (Osaka, JP)
Assignee: Sumitomo Electric Industries, Ltd.
H01L29/1608H01L21/3065H01L29/045H01L29/42364H01L29/66068H01L29/7802H01L21/0475H01L29/7813
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Quick Facts
Patent No.
US 9,647,072
App. No.
14/441,022
Granted
May 9, 2017
Kind
B2
Abstract

A silicon carbide semiconductor device has a silicon carbide substrate, a gate insulating film, and a gate electrode. Silicon carbide substrate includes a first impurity region having a first conductivity type, a well region being in contact with the first impurity region and having a second conductivity type which is different from the first conductivity type, and a second impurity region separated from the first impurity region by the well region and having the first conductivity type. The gate insulating film is in contact with the first impurity region and the well region. The gate electrode is in contact with the gate insulating film and is arranged opposite to the well region with respect to the gate insulating film. A specific on-resistance at a voltage which is half a gate driving voltage applied to the gate electrode is smaller than twice the specific on-resistance at the gate driving voltage.

Claims (16)

1. A silicon carbide semiconductor device, comprising:

a silicon carbide substrate including a first impurity region having a first conductivity type, a well region being in contact with said first impurity region and having a second conductivity type which is different from said first conductivity type, and a second impurity region being separated from said first impurity region by said well region and having said first conductivity type;

a gate insulating film being in contact with said first impurity region and said well region; and

a gate electrode being in contact with said gate insulating film and being arranged opposite said to said well region with respect to said gate insulating film,

a specific on-rsistance at a voltage which is half a gate driving voltage applied to said gate electrode being smaller than twice said specific on-resistance at said gate driving voltage,

wherein a surface of said well region in contact with said gate insulating film includes a first plane having a plane orientation of {0-33-8} microscopically and a second plane having a plane orientation of {0-11-1} microscopically, said first plane and said second plane of said surface constituting a complex plane having a plane orientation of {0-11-2}.

2. The silicon carbide semiconductor device according to claim 1 , wherein a threshold voltage of a gate voltage is greater than or equal to 5% of said gate driving voltage.

3. The silicon carbide semiconductor device according to claim 1 , wherein said gate driving voltage is greater than or equal to 10V and less than or equal to 20V.

4. The silicon carbide semiconductor device according to claim 1 , wherein said specific on-resistance is a value measured at a room temperature.

5. A silicon carbide semiconductor device, comprising:

a silicon carbide substrate including a first impurity region having a first conductivity type, a well region being in contact with said first impurity region and having a second conductivity type which is different from said first conductivity type, and a second impurity region being separated from said first impurity region by said well region and having said first conductivity type;

a gate insulating film being in contact with said first impurity region and said well region; and

a gate electrode being in contact with said gate insulating film and being arranged opposite side to said well region with respect to said gate insulating film,

a specific on-resistance at a voltage which is half a gate driving voltage applied to said gate electrode being smaller than twice said specific on-resistance at said gate driving voltage,

wherein a surface of said well region in contact with said gate insulating film includes a first plane having a plane orientation of {0-33-8} microscopically and a second plane having a plane orientation of {0-11-1} microscopically, said first plane and said second plane of said surface constituting a complex plane having a plane orientation of {0-11-2}, and

wherein said surface has an off angle of 62°±10° with respect to a {000-1} plane macroscopically.

Assignments (2)
NUNC PRO TUNC ASSIGNMENT Recorded Jul 1, 2026
From: SUMITOMO ELECTRIC INDUSTRIES, LTD.
To: MITSUMI ELECTRIC CO., LTD.
Reel/Frame 075871/0320 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 6, 2015
From: HIYOSHI, TORU; MASUDA, TAKEYOSHI; WADA, KEIJI; TSUNO, TAKASHI
To: SUMITOMO ELECTRIC INDUSTRIES, LTD.
Reel/Frame 035576/0992 →
Priority Claims (1)
JP 2012-275754 · Dec 18, 2012 · national
Continuity (1)
Related Publication 20150303266A1 · Oct 22, 2015