IP Library › Granted Patent US 9,647,075
Granted Patent B2
US 9,647,075 · App. 14/856,154 · Granted May 9, 2017

Segmented field plate structure

Inventors: Jenn Hwa Huang (Chandler, AZ); Tianwei Sun (Tempe, AZ); James A. Teplik (Mesa, AZ)
Assignee: NXP USA, INC.
H01L29/404H01L21/3205H01L29/402H01L29/78H01L23/485H01L27/0623H01L29/2003H01L29/7783H01L29/7787
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,647,075
App. No.
14/856,154
Granted
May 9, 2017
Kind
B2
Abstract

A device includes a transistor formed over a substrate. The transistor includes a source structure, a drain structure, and a gate structure. A dielectric layer is formed over the transistor, and a plurality of vias are electrically connected to the source structure. A metal layer is formed over the dielectric layer. The metal layer includes a field plate over the gate structure, a plurality of contact pads over each via, and a plurality of fingers interconnecting each one of the plurality of contact pads to the field plate.

Claims (30)

1. A device, comprising:

a transistor formed over a substrate, the transistor includes a source structure, a drain structure, and a gate structure;

a dielectric layer over the transistor;

a plurality of vias electrically connected to the source structure; and

a metal layer over the dielectric layer, the metal layer including:

a field plate over the gate structure, the field plate including a notch over the gate structure,

a plurality of contact pads over each via, and

a plurality of fingers interconnecting each one of the plurality of contact pads to the field plate.

2. The device of claim 1 , wherein each one of the plurality of fingers is directly connected to one and only one of contact pads.

3. The device of claim 1 , wherein each one of the plurality of fingers has a width of about 5 um to 10 um.

4. The device of claim 1 , wherein the plurality of fingers are separated from one another by at least about 5 um.

5. The device of claim 1 , wherein the notch has a width of about 5 um to 10 um.

6. The device of claim 1 , wherein the metal layer forms a metal contact over the substrate, the metal contact being electrically connected to the drain structure.

7. The device of claim 1 , wherein the transistor is a gallium nitride field effect transistor.

8. A device, comprising:

a transistor formed over a substrate;

a dielectric layer over the transistor; and

a metal layer over the dielectric layer, the metal layer including:

a plurality of contact pads electrically connected to a first structure of the transistor,

a metal contact electrically connected to a second structure of the transistor, and

a field plate, the field plate being electrically connected to the plurality of contact pads and not electrically connected to the metal contact, the field plate including a notch over a gate structure of the transistor.

9. The device of claim 8 , wherein the plurality of contact pads, metal contact, and field plate are formed by patterning the metal layer.

10. The device of claim 8 , wherein the metal layer includes a plurality of fingers connecting the field plate to each of the plurality of contact pads.

11. The device of claim 10 , wherein each one of the plurality of fingers has a width of about 5 um to 10 um.

12. The device of claim 10 , wherein each one of the plurality of fingers are separated by at least about 5 um.

13. The device of claim 8 , wherein the field plate defines an opening over a third structure of the transistor.

14. The device of claim 13 , wherein the opening has a width of about 5 um to 10 um.

15. The device of claim 8 , wherein the notch has a width of about 5 um to 10 um.

16. The device of claim 8 , wherein the transistor is a gallium nitride field effect transistor.

17. The device of claim 8 , wherein the first structure is characterized as a source structure of the transistor, and the second structure is characterized as a drain structure of the transistor.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 16, 2015
From: HUANG, JENN HWA; SUN, TIANWEI; TEPLIK, JAMES A.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 036582/0697 →
Continuity (1)
Related Publication 20170077245A1 · Mar 16, 2017