Semiconductor device having contact plug in two dielectric layers and two etch stop layers
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a plurality of gate structures on the substrate; forming a first stop layer on the gate structures; forming a second stop layer on the first stop layer; forming a first dielectric layer on the second stop layer; forming a plurality of first openings in the first dielectric layer to expose the second stop layer; forming a plurality of second openings in the first dielectric layer and the second stop layer to expose the first stop layer; and removing part of the second stop layer and part of the first stop layer to expose the gate structures.
1. A semiconductor device, comprising:
a substrate;
a plurality of gate structures on the substrate;
an interlayer dielectric (ILD) layer around the gate structures;
a first etch stop layer on the ILD layer and the gate structures;
a first dielectric layer on the first etch stop layer;
a second etch stop layer on the first dielectric layer;
a second dielectric layer on the second etch stop layer;
a plurality of first contact plugs in the ILD layer, the first etch stop layer, and the first dielectric layer for electrically connecting to a source/drain region in the substrate;
a plurality of second contact plugs in the second etch stop layer and the second dielectric layer for electrically connecting to the first contact plugs, wherein the top surfaces of the second contact plugs and the second dielectric layer are coplanar and a bottom surface of the second contact plugs is greater than a top surface of the first contact plugs; and
a plurality of third contact plugs in the first etch stop layer, the first dielectric layer, the second etch stop layer, and the second dielectric layer for electrically connecting to the gate structures, wherein the third contact plugs contact the gate structures and the first contact plugs directly.
2. The semiconductor device of claim 1 , wherein the gate structures comprise metal gates.
3. The semiconductor device of claim 1 , wherein the first etch stop layer and the second etch stop layer comprise silicon nitride.
4. The semiconductor device of claim 1 , wherein the first dielectric layer and the second dielectric layer comprise silicon oxide.
5. The semiconductor device of claim 1 , wherein the second dielectric layer contacts the second etch stop layer directly.
6. The semiconductor device of claim 1 , wherein a top surface of the third contact plugs is equal to a bottom surface of the third contact plugs.