Shallow trench isolation trenches and methods for NAND memory
A NAND memory is provided that includes a memory cell region and a peripheral region. The peripheral region includes a shallow trench isolation trench disposed in a substrate. The shallow trench isolation trench has a first tab extension and a second tab extension. The first tab extension is disposed at a top portion of the shallow trench isolation trench, and extends in a first direction from the shallow trench isolation trench. The second tab extension is disposed at a top portion of the shallow trench isolation trench, and extends in a second direction from the shallow trench isolation trench.
1. A method of forming a NAND memory, the method comprising:
forming a memory cell region in a substrate;
forming a peripheral region in the substrate adjacent the memory cell region;
forming a shallow trench isolation trench in the substrate in the peripheral region by:
forming a dielectric material over the substrate;
removing a portion of the dielectric material to form an exposed portion of the substrate;
etching the exposed portion of the substrate to form a first tab extension and a second tab extension at a top portion of the shallow trench isolation trench, the first tab extension extending in a first direction from the shallow trench isolation trench, the second tab extension extending in a second direction from the shallow trench isolation trench; and
etching the substrate downward from the first tab extension and the second tab extension to form a trench,
wherein a bottom surface of a first portion of the dielectric material comprises a top surface of the first tab extension, and a bottom surface of a second portion of the dielectric material comprises a top surface of the second tab extension.
2. The method of claim 1 , wherein:
forming the first tab extension comprises forming the first tab extension to extend substantially horizontally outward from the shallow trench isolation trench; and
forming the second tab extension comprises forming the second tab extension to extend substantially horizontally outward from the shallow trench isolation trench.
3. The method of claim 1 , wherein the first tab extension and the second tab extension each have a length of between about 50 angstroms and about 500 angstroms.
4. The method of claim 1 , wherein the first tab extension and the second tab extension each have a height of between about 50 angstroms and about 500 angstroms.
5. The method of claim 1 , wherein the shallow trench isolation trench comprises a dielectric material.
6. The method of claim 1 , wherein the shallow trench isolation trench comprises one or more of silicon dioxide, silicon nitride, silicon oxynitride, and low K dielectrics.
7. The method of claim 1 , wherein the peripheral region comprises a transistor region and a capacitor region, and the method comprises forming the shallow trench isolation trench between the transistor region and the capacitor region.
8. A method of forming a shallow trench isolation trench in a substrate of a peripheral region of a NAND memory, the method comprising:
forming a first dielectric material layer on the substrate;
etching the first dielectric material layer to expose a region of the substrate;
etching the exposed region of the substrate to form a first trench tab recess that extends under an exposed underside of a first portion of the first dielectric material layer and a second trench tab recess that extends under an exposed underside of a second portion of the first dielectric material layer;
etching vertically downward from the first trench tab recess and the second trench tab recess to form a trench; and
forming a second dielectric material in the first trench tab recess, the second trench tab recess and the trench.
9. The method of claim 8 , wherein the first trench tab recess and the second trench tab recess each have a length of between about 50 angstroms and about 500 angstroms.
10. The method of claim 8 , wherein the first trench tab recess and the second trench tab recess each have a height of between about 50 angstroms and about 500 angstroms.
11. The method of claim 8 , wherein the trench has a height of between about 1000 angstroms and about 3000 angstroms.
12. The method of claim 8 , wherein the second dielectric material layer comprises one or more of silicon dioxide, silicon nitride, silicon oxynitride, and low K dielectrics.
13. The method of claim 8 , wherein the peripheral region of the NAND memory comprises a transistor region and a capacitor region, and the method comprises forming the shallow trench isolation trench between the transistor region and the capacitor region.