System and method of filtering actual defects from defect information for a wafer

1. A method of generating a set of defect candidates for a wafer, the wafer comprising at least one die manufactured according to a mask, the mask being prepared by combining a plurality of layout areas, the method comprising:

receiving an initial defect information from a wafer scanning device indicating potential defects of a semiconductor wafer, wherein the potential defects include actual defects and false defects;

determining a boundary region on the semiconductor wafer;

creating an exclusion region from the boundary region, the exclusion region having a first set of actual defects in the potential defects of the semiconductor wafer; and

creating filtered defect information by removing the first set of actual defects from the initial defect information.

2. The method of claim 1 , wherein the exclusion region is a rectangular annulus formed from the boundary region.

3. The method of claim 1 , wherein the exclusion region is compiled in a graphic data format recognizable by a layout software program.

4. The method of claim 3 , further comprising displaying the filtered defect information via the layout software program.

5. The method of claim 1 , wherein the boundary region defines a single integrated circuit that is independent of any other integrated circuits on the wafer.

6. The method of claim 5 , wherein the first set of defects comprises at least one false defect that will not affect functionality of an integrated circuit.

7. The method of claim 6 , wherein the at least one false defect comprises a discolored material formed due to a process variation, the discolored material having an optical characteristic that is similar to an actual defect.

8. The method of claim 5 , wherein the first set of defects comprises at least one actual defect that does not affect performance of the single integrated circuit.

9. The method of claim 1 , wherein the boundary region lacks layout patterns associated with an integrated circuit.

10. A non-transitory computer readable storage medium encoded with a computer program code, the computer program code being arranged to cause a hardware processor to:

receive an initial defect information from a wafer scanning device indicating potential defects of a semiconductor wafer, wherein the potential defects include actual defects and false defects;

determine a boundary region on the semiconductor wafer;

create an exclusion region from the boundary region, the exclusion region having a first set of actual defects in the potential defects of the semiconductor wafer; and

create filtered defect information by removing the first set of actual defects from the initial defect information.

11. The computer readable storage medium of claim 10 , wherein the exclusion region is a rectangular annulus formed from the boundary region.

12. The computer readable storage medium of claim 10 , wherein the exclusion region is compiled in a graphic data format recognizable by a layout software program.

13. The computer readable storage medium of claim 12 , wherein the layout software program is configured to display the filtered defect information.

14. The computer readable storage medium of claim 10 , wherein the boundary region defines a single integrated circuit that is independent of any other integrated circuits on the wafer.

15. The computer readable storage medium of claim 14 , wherein the first set of defects comprises at least one false defect that will not affect functionality of an integrated circuit.

16. The computer readable storage medium of claim 15 , wherein the at least one false defect comprises a discolored material formed due to a process variation, the discolored material having an optical characteristic that is similar to an actual defect.

17. The computer readable storage medium of claim 14 , wherein the first set of defects comprises at least one actual defect that will not affect functionality of the single integrated circuit.

18. The computer readable storage medium of claim 10 , wherein the boundary region lacks layout patterns associated with an integrated circuit.

19. A wafer inspection system, comprising:

a wafer inspection device configured to scan a semiconductor wafer and generate initial defect information indicating potential defects of the semiconductor wafer, wherein the potential defects include actual defects and false defects;

a hardware processor configured to receive the initial defect information, to determine a boundary region on the semiconductor wafer, to create an exclusion region from the boundary region, the exclusion region having a first set of actual defects in the potential defects of the semiconductor wafer, and to create filtered defect information by removing the first set of actual defects from the initial defect information; and

a display configured to display the first set of actual defects.

20. The wafer inspection system of claim 19 , wherein the boundary region is a rectangular annulus region defining a single integrated circuit that is independent of any other integrated circuits on the wafer, and

wherein the first set of defects comprises at least one false defect that will not affect the functionality of the integrated circuit or at least one actual defect that will not affect the functionality of the integrated circuit.