Content-addressable memory having multiple reference matchlines to reduce latency
Words of data are maintained in content-addressable memory cells arranged in rows. Two of the rows are timing reference rows, and the remainder of the rows are data rows that maintain the words of data. The data rows form individual matchlines. A first of the reference rows forms a precharge reference matchline, and a second of the reference rows forms an evaluation reference matchline. The timing for the individual matchlines to precharge is based on the time to precharge the precharge reference matchline, and timing for the individual matchlines to evaluate a search word is based on the time for the evaluation reference matchline to evaluate the search word.
1. A device comprising:
content-addressable memory cells arranged in rows, two of the rows are timing reference rows and the remainder of the rows are data rows maintaining words of data,
the data rows comprise individual matchlines,
a first reference row of the reference rows comprises a precharge reference matchline,
a second reference row of the reference rows comprises an evaluation reference matchline,
the precharge reference matchline is hardwired to match all bits and timing for the individual matchlines to precharge is based on a time to precharge the precharge reference matchline, and
the evaluation reference matchline is hardwired to a one-bit-miss word that has only one bit not producing a match and timing for the individual matchlines to evaluate a search word is based on a time for the evaluation reference matchline to evaluate the search word.
2. The device according to claim 1 , further comprising a controller connected to the individual matchlines, the precharge reference matchline, and the evaluation reference matchline,
the controller determines when a precharging operation of the individual matchlines is completed based upon a precharging operation being completed within the precharge reference matchline, and
the controller determines when an evaluation operation of the individual matchlines is completed based upon an evaluation operation being completed within the evaluation reference matchline.
3. The device according to claim 1 , the time to precharge the precharge reference matchline and the time to evaluate the evaluation reference matchline are not fixed times and are variable times based upon processing conditions including voltage, temperature, material make up of the device, size of the device, and resistance of the device.
4. The device according to claim 1 , further comprising searchlines intersecting the data rows, the searchlines evaluate search words by broadcasting the search words to the data rows.
5. The device according to claim 1 , each of the rows maintains a single one of the words of data.
6. A device comprising:
content-addressable memory cells arranged in rows, two of the rows are timing reference rows and the remainder of the rows are data rows maintaining words of data, the data rows comprise individual matchlines, a first reference row of the reference rows comprises a precharge reference matchline, and a second reference row of the reference rows comprises an evaluation reference matchline;
first-type of sense amplifiers connected to the individual matchlines and the evaluation reference matchline; and
a second-type of sense amplifier, different from the first-type of sense amplifiers, connected to the precharge reference matchline,
the precharge reference matchline is hardwired to match all bits and timing for the individual matchlines to precharge is based on a time to precharge the precharge reference matchline, and
the evaluation reference matchline is hardwired to a one-bit-miss word that has only one bit not producing a match and timing for the individual matchlines to evaluate a search word is based on a time for the evaluation reference matchline to evaluate the search word.
7. The device according to claim 6 , a location within the content-addressable memory cells is output in response to the search word being matched to the words of data during evaluation of the individual matchlines.
8. The device according to claim 6 , a location within the content-addressable memory cells is output in response to the search word being matched to the words of data during evaluation of the individual matchlines.
9. The device according to claim 6 , further comprising a controller connected to the individual matchlines, the precharge reference matchline, and the evaluation reference matchline,
the controller determines when a precharging operation of the individual matchlines is completed based upon a precharging operation being completed within the precharge reference matchline, and
the controller determines when an evaluation operation of the individual matchlines is completed based upon an evaluation operation being completed within the evaluation reference matchline.
10. The device according to claim 6 , the time to precharge the precharge reference matchline and the time to evaluate the evaluation reference matchline are not fixed times and are variable times based upon processing conditions including voltage, temperature, material make up of the device, size of the device, and resistance of the device.
11. The device according to claim 6 , further comprising searchlines intersecting the data rows, the searchlines evaluate search words by broadcasting the search words to the data rows.
12. The device according to claim 6 , each of the rows maintains a single one of the words of data.
13. A method comprising:
maintaining words of data in content-addressable memory cells arranged in rows, two of the rows are timing reference rows and the remainder of the rows are data rows maintaining the words of data, the data rows comprise individual matchlines, a first reference row of the reference rows comprises a precharge reference matchline, and a second reference row of the reference rows comprises an evaluation reference matchline;
determining timing for the individual matchlines to precharge based on a time to precharge the precharge reference matchline, where the precharge reference matchline is hardwired to match all bits; and
determining timing for the individual matchlines to evaluate a search word based on a time for the evaluation reference matchline to evaluate the search word, where the evaluation reference matchline is hardwired to a one-bit-miss word that has only one bit not producing a match.
14. The method according to claim 13 , the determining timing for the individual matchlines to precharge comprises determining when a precharging operation of the individual matchlines is completed based upon a precharging operation being completed within the precharge reference matchline, using a controller connected to the individual matchlines, the precharge reference matchline, and the evaluation reference matchline; and
the determining timing for the individual matchlines to evaluate a search word comprises determining when an evaluation operation of the individual matchlines is completed based upon an evaluation operation being completed within the evaluation reference matchline, using the controller.
15. The method according to claim 13 , the time to precharge the precharge reference matchline and the time to evaluate the evaluation reference matchline are not fixed times and are variable times based upon processing conditions including voltage, temperature, material make up of the content-addressable memory cells, size of the content-addressable memory cells, and resistance of the content-addressable memory cells.
16. The method according to claim 13 , evaluating the search word comprises broadcasting the search words to the data rows using searchlines intersecting the data rows.