Flat STI surface for gate oxide uniformity in Fin FET devices

1. A method of fabricating a fin field-effect transistor (Fin FET) device, the method comprising:

providing a substrate having a fin structure, an upper portion of the fin structure having a first fin surface profile;

forming an isolation region on the substrate and in contact with the fin structure;

recessing at least a portion of the isolation region by an etch process to form a recessed portion and to expose the upper portion of the fin structure, the recessed portion having a first isolation surface profile;

applying a thermal hydrogen treatment consisting essentially of hydrogen gas to the fin structure and the recessed portion; and

forming a gate dielectric layer with a substantially uniform thickness over the fin structure,

wherein the thermal hydrogen treatment provides:

the upper portion of the fin structure with a second surface profile, the second surface profile including a top surface of the fin structure having substantially rounded corners being defined by a first radius of curvature relating to a fraction of a width of a channel region in the fin structure which is curved along the top surface and a second radius of curvature relating to a fraction of a height of the channel region which is curved along sidewalls of the fin structure; and

the isolation region with a second surface profile having a substantially flat step height, the substantially flat step height being defined by a downward slope from sidewalls of the fin structure toward a top surface of the isolation region which relates to a fraction of the height of the channel region.

2. The method of claim 1 , wherein applying the thermal hydrogen treatment comprises flowing the hydrogen gas with a gas flow rate in a range of 0.2 standard-liter-per-minute (slm) to 50 slm.

3. The method of claim 1 , wherein the thermal hydrogen treatment is applied with a temperature in a range of 750 degrees Celsius to 1000 degrees Celsius.

4. The method of claim 1 , wherein the thermal hydrogen treatment is applied with a pressure in a range of 0.2 Torr to 760 Torr.

5. The method of claim 1 , wherein the thermal hydrogen treatment is applied for a duration in a range of 20 seconds to 120 seconds.

6. The method of claim 1 , wherein:

in the forming the gate dielectric layer, the gate dielectric layer is formed to have a first thickness at a top surface of the recessed portion, a second thickness at a top surface of the fin structure, and a third thickness at one or more sidewalls of the fin structure, and

the first thickness, the second thickness and the third thickness vary from one another by less than 0.3 nanometers.

7. The method of claim 1 , further comprising:

forming a gate structure over at least a portion of the fin structure and over the isolation region;

forming a second recessed portion by etching a part of the fin structure; and

forming an epitaxial layer in and above the second recessed portion.

8. The method of claim 1 , wherein:

the first fin surface profile includes square edges at the upper portion of the fin structure,

the first isolation surface profile includes substantially round edges at an upper portion of the recessed portion, and

the second isolation surface profile includes square edges at the upper portion of the recessed portion.

9. A method of fabricating a fin field-effect transistor (Fin FET) device, the method comprising:

providing a substrate having fin structures, an upper portion of each of the fin structures having a first fin surface profile;

forming an isolation region on the substrate such that the fin structures are embedded in the isolation region;

recessing at least a portion of the isolation region by an etch process to form a recessed portion and to expose upper portions of the fin structures, the recessed portion having a first isolation surface profile between adjacent two fin structures;

applying a thermal hydrogen treatment consisting essentially of hydrogen gas to the fin structures and the recessed portion; and

forming a gate dielectric layer with a substantially uniform thickness over the exposed upper portions of fin structures,

wherein the recessed portion is adjusted from the first isolation surface profile to a second isolation surface profile and the upper portions of the fin structures are provided with a second surface profile including a top surface of the fin structure having corners with a radius of curvature R, where 0.1 W<R<0.2 W, where W is a width of a channel region in the fin structure, by the thermal hydrogen treatment.

10. The method of claim 9 , wherein:

the first fin surface profile includes square edges at the upper portion of the fin structure,

the first isolation surface profile includes substantially round edges at an upper portion of the recessed portion, and

the second isolation surface profile includes square edges at the upper portion of the recessed portion.

11. The method of claim 10 , wherein applying the thermal hydrogen treatment comprises flowing the hydrogen gas with a gas flow rate in a range of 0.2 standard-liter-per-minute (slm) to 50 slm.

12. The method of claim 9 , wherein the thermal hydrogen treatment is applied with a temperature in a range of 750 degrees Celsius to 1000 degrees Celsius.

13. The method of claim 9 , wherein the thermal hydrogen treatment is applied with a pressure in a range of 0.2 Torr to 760 Torr.

14. The method of claim 9 , wherein the thermal hydrogen treatment is applied for a duration in a range of 20 seconds to 120 seconds.

15. The method of claim 9 , wherein:

in the forming the gate dielectric layer, the gate dielectric layer is formed to have a first thickness at a top surface of the recessed portion, a second thickness at a top surface of the fin structure, and a third thickness at one or more sidewalls of the fin structure, and

the first thickness, the second thickness and the third thickness vary from one another by less than 0.3 nanometers.

16. The method of claim 9 , further comprising:

forming a gate structure over at least a portion of the fin structure and over the isolation region;

forming a second recessed portion by etching a part of the fin structure; and

forming an epitaxial layer in and above the second recessed portion.

17. A semiconductor device, comprising:

a substrate;

a fin structure having a top surface with substantially rounded corners, the substantially rounded corners being defined by a first radius of curvature relating to a fraction of a width of a channel region in the fin structure which is curved along the top surface and a second radius of curvature relating to a fraction of a height of the channel region which is curved along sidewalls of the fin structure;

an isolation region formed over the substrate and in contact with at least a sidewall of the fin structure, the isolation region having a top surface with a substantially flat step height based on a thermal hydrogen treatment, the substantially flat step height being defined by a downward slope from the sidewalls of the fin structure toward the top surface of the isolation region which relates to a fraction of the height of the channel region; and

a gate dielectric layer formed in contact with the fin structure and the top surface of the isolation region, the gate dielectric layer having a thickness that is substantially uniform over the fin structure and the isolation region based on the thermal hydrogen treatment.

18. The semiconductor device of claim 17 , wherein:

the gate dielectric layer has a first thickness at the top surface of the isolation region,

the gate dielectric layer has a second thickness at the top surface of the fin structure,

the gate dielectric layer has a third thickness at one or more sidewalls of the fin structure, and

the first thickness, the second thickness and the third thickness vary from one another by less than 0.3 nanometers.

19. The semiconductor device of claim 17 , further comprising:

a gate stack including a gate electrode layer and the gate dielectric layer, the gate stack covering a portion of the fin structure; and

a source and a drain, each including a stressor layer disposed in and over recessed portions formed in the fin structure, the stressor layer applying a stress to a channel region of the fin structure covered by the gate stack.