IP Library Granted Patent US 9,741,448
Granted Patent B2
US 9,741,448 · App. 15/371,127 · Granted Aug 22, 2017

Three-dimensional offset-printed memory with multiple bits-per-cell

Inventor: Guobiao Zhang (Corvallis, OR)
Assignees: HangZhou HaiChun Information Technology Co., Ltd.; Guobiao Zhang
G11C17/18G11C17/00G11C17/06G11C17/16H01L27/1021H01L27/11206G11C2213/71
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Quick Facts
Patent No.
US 9,741,448
App. No.
15/371,127
Granted
Aug 22, 2017
Kind
B2
Abstract

The present invention discloses a three-dimensional offset-printed memory (3D-oP) with multiple bits-per-cell. The mask-patterns for different bits-in-a-cell are merged onto a same data-mask. At different printing steps, a wafer is offset by different values with respect to the data-mask. Accordingly, data-patterns from a same data-mask are printed into different bits-in-a-cell.

Claims (25)

1. A three-dimensional offset-printed memory (3D-oP) with multiple bits-per-cell, comprising:

a semiconductor substrate;

at least a memory level stacked above and coupled to said substrate, said memory level comprising at least two data-coding layers storing at least two data-arrays;

wherein all 3D-oP devices in a same 3D-oP batch have a same data-array set; and at least two 3D-oP devices in said batch have different data-array sequences.

2. The 3D-oP according to claim 1 , further comprising a configurable-output for configuring the output of said memory based on the data-array sequence in said memory.

3. The 3D-oP according to claim 2 , wherein said configurable-output further comprises a storage means for storing an information related to the data-array sequence.

4. The 3D-oP according to claim 3 , wherein said storage means is a non-volatile writable memory.

5. The 3D-oP according to claim 1 , wherein said 3D-oP batch further includes first and second 3D-oP devices:

said two data-coding layers of said first 3D-oP device including first and second data-coding layers with said second data-coding layer located above said first data-coding layer, said first data-coding layer storing a first data-array and said second data-coding layer storing a second data-array; and

said two data-coding layers of said second 3D-oP device including third and fourth data-coding layers with said fourth data-coding layer located above said third data-coding layer, said fourth data-coding layer storing said first data-array and said third data-coding layer storing said second data-array.

6. The 3D-oP according to claim 5 , wherein said first or second 3D-oP device further comprises a configurable-output for configuring the output of said 3D-oP device based on the data-array sequence.

7. The 3D-oP according to claim 1 , wherein said 3D-oP batch further includes first and second 3D-oP devices:

said first 3D-oP device comprising first and second memory levels with said second memory level located above said first memory level, said first memory level comprising a first data-coding layer storing said first data-array, said second memory level comprising a second data-coding layer storing said second data-array; and

said second 3D-oP device comprising third and fourth memory levels with said fourth memory level located above said third memory level, said third memory level comprising a third data-coding layer storing said second data-array, said fourth memory level comprising a fourth data-coding layer storing said first data-array.

8. The 3D-oP according to claim 7 , wherein said first or second 3D-oP device further comprises a configurable-input for configuring the input of said 3D-oP device based on the data-array sequence.

9. The 3D-oP according to claim 1 belonging to a three-dimensional memory package, wherein said memory package comprises a plurality of vertically stacked 3D-oP dice.

10. The 3D-oP according to claim 1 , wherein a data-patterns in said data-coding layers are formed using photo-lithography.

11. The 3D-oP according to claim 1 , wherein a data-patterns in said data-coding layers are formed using imprint-lithography.

12. A batch of three-dimensional offset-printed memory (3D-oP) with multiple bits-per-cell, comprising first and second 3D-oP devices, wherein:

said first 3D-oP device comprises a first memory level, said first memory level comprising first and second data-coding layers with said second data-coding layer located above said first data-coding layer, said first data-coding layer storing a first data-array and said second data-coding layer storing a second data-array; and

said second 3D-oP device comprises a second memory level, said second memory level comprising third and fourth data-coding layers with said fourth data-coding layer located above said third data-coding layer, said fourth data-coding layer storing said first data-array and said third data-coding layer storing said second data-array.

13. The batch of 3D-oP according to claim 12 , wherein said first or second 3D-oP device further comprises a configurable-output for configuring the output of said 3D-oP device based on the data-array sequence.

14. The batch of 3D-oP according to claim 13 , wherein said configurable-output further comprises a storage means for storing an information related to the data-array sequence.

15. The batch of 3D-oP according to claim 14 , wherein said storage means is a non-volatile writable memory.

16. The batch of 3D-oP according to claim 12 belonging to a three-dimensional memory package, wherein said memory package comprises a plurality of vertically stacked 3D-oP dice.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 23, 2025
From: ZHANG, GUOBIAO, DR.
To: HANGZHOU HAICUN INFORMATION TECHNOLOGY CO., LTD.
Reel/Frame 070917/0043 →
Priority Claims (1)
CN 2016 1 0927672 · Oct 24, 2016 · national
Continuity (4)
Continuation 14876908 · Oct 7, 2015
Continuation 13599085 · Aug 30, 2012
Provisional Application 61529920 · Sep 1, 2011
Related Publication 20170084348A1 · Mar 23, 2017