Stacked semiconductor package and manufacturing method thereof
Disclosed herein is a stacked semiconductor package in which semiconductor chips having various sizes are stacked. In accordance with one aspect of the present disclosure, a stacked semiconductor package includes a first semiconductor chip structure provided with a first semiconductor chip, a first mold layer surrounding the first semiconductor chip, and a first penetration electrode passing through the first mold layer and electrically connected to the first semiconductor chip, and a second semiconductor chip structure vertically stacked on the first semiconductor chip structure and provided with a second semiconductor chip and a second penetration electrode electrically connected to the first penetration electrode, wherein the first semiconductor chip structure may have the same size as the second semiconductor chip structure.
1. A stacked semiconductor package comprising:
a first semiconductor chip structure provided with a first semiconductor chip, a first mold layer surrounding the first semiconductor chip, and a first penetration electrode passing through the first mold layer and electrically connected to the first semiconductor chip; and
a second semiconductor chip structure vertically stacked on the first semiconductor chip structure and provided with a second semiconductor chip and a second penetration electrode passes through the second semiconductor chip electrically connected to the first penetration electrode, wherein the first penetration electrode and the second penetration electrode are disposed on the same position,
wherein the first semiconductor chip has a different width from the second semiconductor chip and the first mold layer has the same width as the second semiconductor chip so that the first semiconductor chip structure has the same width as the second semiconductor chip structure.
2. The stacked semiconductor package of claim 1 , wherein at least one side of the first mold layer has the same width as at least one side of the second semiconductor chip structure.
3. The stacked semiconductor package of claim 1 , wherein one side of the first semiconductor chip has the same width as one side of the second semiconductor chip.
4. The stacked semiconductor package of claim 1 , wherein the first semiconductor chip structure is stacked to be disposed on the upper side of the second semiconductor chip structure.
5. The stacked semiconductor package of claim 1 , wherein the second semiconductor chip structure is stacked to be disposed on the upper side of the first semiconductor chip structure.
6. The stacked semiconductor package of claim 1 , wherein an active surface of the first semiconductor chip is disposed to face the second semiconductor chip.
7. The stacked semiconductor package of claim 1 , wherein an active surface of the first semiconductor chip is disposed to be opposite to the second semiconductor chip.
8. The stacked semiconductor package of claim 1 , wherein the first semiconductor chip comprises a first chip pad, and the first semiconductor chip structure further comprises a rerouting pattern configured to connect the first chip pad of the first semiconductor chip to the first penetration electrode and formed on the first mold layer.
9. The stacked semiconductor package of claim 1 , wherein the second semiconductor chip structure further comprises a second mold layer surrounding the second semiconductor chip.
10. The stacked semiconductor package of claim 1 , wherein the stacked semiconductor package further comprises a third semiconductor chip structure vertically stacked on the first semiconductor chip structure or the second semiconductor chip structure, wherein the third semiconductor chip structure has the same width as the first semiconductor chip structure or the second semiconductor chip structure.
11. The stacked semiconductor package of claim 10 , wherein the third semiconductor chip structure comprises a third semiconductor chip, a third mold layer surrounding the third semiconductor chip, and a third penetration electrode passing through the third mold layer.
12. The stacked semiconductor package of claim 11 , wherein the third semiconductor chip has a different width from at least one of the first semiconductor chip and the second semiconductor chip.
13. A manufacturing method for a stacked semiconductor package comprising:
forming a first mold layer surrounding a first semiconductor chip, forming a first penetration electrode passing through the first mold layer, forming a stacked semiconductor package by forming a rerouting pattern on the first mold layer to connect the first penetration electrode to the first chip pad,
stacking a second semiconductor chip structure having a second semiconductor chip and a second penetration electrode on the first semiconductor chip structure, wherein the second penetration electrodes passes through the second semiconductor chip and
electrically connecting the first penetration electrode of the first semiconductor chip structure to the second penetration electrode of the second semiconductor chip structure, wherein the first semiconductor chip has a different width from the second semiconductor chip and the first mold layer has the same width as the second semiconductor chip so that the first semiconductor chip structure has the same width as the second semiconductor chip.
14. A stacked semiconductor package comprising:
a first semiconductor chip structure provided with a first semiconductor chip, a first mold layer surrounding the first semiconductor chip, and a first penetration electrode passing through the first mold layer and electrically connected to the first semiconductor chip; and
a second semiconductor chip vertically stacked on the first semiconductor chip structure and provided with a second penetration electrode electrically connected to the first penetration electrode, wherein the second penetration electrode passes through the second semiconductor chip,
wherein the first semiconductor chip and the second semiconductor chip have different width and the first mold layer has the same width as the second semiconductor chip so that the first semiconductor chip structure has the same width as the second semiconductor chip structure, and at least one side of the first mold layer has the same width as at least one side of the second semiconductor chip.
15. The stacked semiconductor package of claim 14 , further comprising an external sealing member sealing the first semiconductor chip structure and the second semiconductor chip.
16. The stacked semiconductor package of claim 15 , wherein the external sealing member includes a material same as the first mold layer.
17. The stacked semiconductor package of claim 15 , wherein the external sealing member includes a material different from the first mold layer.