Power converter package with integrated output inductor
In one implementation, a semiconductor package includes a first patterned conductive carrier including partially etched segments. The semiconductor package also includes a control FET having a control drain attached to a first partially etched segment of the first patterned conductive carrier. In addition, the semiconductor package includes a sync FET having a sync source and a sync gate attached to respective second and third partially etched segments of the first patterned conductive carrier. The semiconductor package further includes a second patterned conductive carrier having a switch node segment situated over a control source of the control FET and over a sync drain of the sync FET, as well as an inductor coupled between the switch node segment and an output segment of the second patterned conductive carrier.
1. A method for fabricating a semiconductor package, said method comprising:
providing a first patterned conductive carrier;
attaching a control drain of a control field-effect transistor (FET) to a first partially etched segment of said first patterned conductive carrier;
attaching a synchronous (sync) source and a sync gate of a sync FET to respective second and third partially etched segments of said first patterned conductive carrier;
attaching a second patterned conductive carrier having a switch node segment for electrically coupling a control source of said control FET to a sync drain of said sync FET; and
coupling an inductor between said switch node segment and an output segment of said second patterned conductive carrier.
2. The method of claim 1 , wherein said first, second, and third partially etched segments of said first patterned conductive carrier are substantially half-etched.
3. The method of claim 1 , wherein said switch node segment of said second patterned conductive carrier is partially etched.
4. The method of claim 1 , wherein said control FET, said sync FET, and said inductor form an output stage of a power converter.
5. The method of claim 1 , wherein at least one of said first patterned conductive carrier and said second patterned conductive carrier comprises at least a portion of a lead frame.
6. The method of claim 1 , wherein said second patterned conductive carrier comprises at least a portion of a lead frame.
7. The method of claim 1 , wherein said control FET and said sync FET comprise silicon power FETs.
8. The method of claim 1 , wherein said control FET and said sync FET comprise group III-Nitride FETs.
9. The method of claim 1 , wherein said control FET and said sync FET comprise group III-Nitride high electron mobility transistors (HEMTs).
10. The method of claim 1 , further comprising attaching a driver integrated circuit for driving at least one of said control FET and said sync FET to a fourth partially etched segment of said first patterned conductive carrier.
11. A method for fabricating a semiconductor package, said method comprising:
providing a first patterned conductive carrier;
attaching a control drain of a control field-effect transistor (FET) to a first partially etched segment of said first patterned conductive carrier;
providing a synchronous (sync) FET having a sync source and a sync gate;
providing a second patterned conductive carrier having a switch node segment situated over a control source of said control FET and over a sync drain of said sync FET for electrically coupling; and
coupling an inductor between said switch node segment and an output segment of said second patterned conductive carrier.
12. The method of claim 11 , wherein said switch node segment of said second patterned conductive carrier is partially etched.
13. The method of claim 11 , wherein said control FET, said sync FET, and said inductor form an output stage of a power converter.
14. The method of claim 11 , wherein at least one of said first patterned conductive carrier and said second patterned conductive carrier comprises at least a portion of a lead frame.
15. The method of claim 11 , wherein said second patterned conductive carrier comprises at least a portion of a lead frame.
16. The method of claim 11 , wherein said control FET and said sync FET comprise silicon power FETs.
17. The method of claim 11 , wherein said control FET and said sync FET comprise group III-Nitride FETs.
18. The method of claim 11 , wherein said control FET and said sync FET comprise group III-Nitride high electron mobility transistors (HEMTs).
19. The method of claim 11 , further comprising:
providing a driver integrated circuit for driving at least one of said control FET and said sync FET.