Algorithmic N search/M write ternary content addressable memory (TCAM)
The present disclosure relates to a content addressable memory (CAM), and more particularly, to an algorithmic ternary content addressable memory (TCAM) that instantiates multiple copies of X-Y TCAMs. The structure includes a content addressable memory (CAM) and an array which instantiates multiple replicated copies of the CAM in a row direction and a column direction of the array.
1. A structure, comprising: a content addressable memory (CAM) instance of a plurality of CAM instances; and a matrix of the plurality of CAM instances which is structured to instantiate multiple replicated copies of the CAM in a row direction of the matrix across a row of the CAM instances and a column direction of the matrix across a column of the CAM instances, wherein each of the plurality of CAM instances is a physical hardware circuit, and the matrix is structured such that multiple operations are captured at a time allowing for a search command to be executed in a first cycle and a write operation to be executed in a second cycle.
2. The structure of claim 1 , wherein the matrix comprises a matrix of 2*M write rows by 2*N search columns of replicated CAMs, where M and N are integer values.
3. The structure of claim 2 , wherein the integer value of N is greater than the integer value of M.
4. The structure of claim 2 , wherein the matrix is structured such that each of 2*N search operations are executed on a corresponding 2*N search column in the 2*M by 2*N matrix to search whether any search key of the 2*N search operations are stored in the matrix.
5. The structure of claim 2 , wherein the matrix is structured such that each of 2*M write operations are executed on a corresponding row of 2*M rows in the 2*M by 2*N matrix.
6. The structure of claim 5 , wherein the matrix is structured such that each of 2*M write operations are executed on the corresponding row of 2*M rows in the 2*M by 2*N matrix in response to at least one search key of a previous 2*N search operation.
7. The structure of claim 5 , wherein the matrix is structured such that each of the 2*M write operations are replicated across the corresponding row of 2*M rows in the 2*M by 2*N matrix.
8. The structure of claim 4 , wherein the matrix is structured such that each search operation is supplied to one of the 2*N search columns and each write operation is supplied to each of the 2*M write rows.
9. The structure of claim 1 , wherein the matrix is structured such that two operations of 2*M writes and 2*N searches are captured every second cycle.
10. The structure of claim 1 , wherein the CAM is one of a ternary CAM (TCAM) and a binary CAM.
11. A structure, comprising a matrix of multiple replicated copies of a content addressable memory (CAM) structure across a plurality of CAM instances in a plurality of write rows and across a plurality of CAM instances in a plurality of search columns structured such that multiple operations are captured at a time allowing for a search command to be executed in the first cycle and a write operation to be executed in the second cycle.
12. The structure of claim 11 , wherein the matrix is structured to allow a comparison between multiple cycles worth of operations to maintain coherency.
13. The structure of claim 11 , wherein the matrix is structured such that the write operation duplicates words across corresponding rows of the CAM structure.
14. The structure of claim 13 , wherein the write operation is executed in the second cycle based on results of any of multiple search operations.
15. The structure of claim 11 , wherein the matrix comprises a matrix of 2*M write rows by 2*N search columns to capture 2*(N+M) operations at a time.
16. The structure of claim 11 , wherein the CAM is one of a ternary CAM (TCAM) and a binary CAM.
17. A method comprising:
executing multiple searches in parallel in replicated CAM instances across a row and a column of a CAM matrix, in a first cycle; and
executing multiple writes or reads in parallel in the replicated CAM instances, in a second cycle,
wherein each of the plurality of replicated CAM instances is a physical hardware circuit.
18. The method of claim 17 , wherein if the writes or searches take multiple cycles, the CAM matrix of the replicated CAM instances will grow rows or columns necessary to accommodate parallelism.
19. The method of claim 18 , wherein the writing operations in each 2*M row occurs in at least the first cycle, and the searching in each column of the 2*N columns occurs in the second or greater cycle.
20. The method of claim 18 , wherein:
the executing of the multiple searches comprise searching for an operation in each column in the CAM matrix which comprises replicating copies of an instance of a CAM; and
the executing of the multiple writes comprises writing a same entry in each replicated copy of the CAM in the row in response to the search operations being returned.