Multi-stage translation of prefetch requests
View Patent ↗A device for multi-stage translation of prefetch requests includes a prefetch queue for providing queued prefetch requests, each of the queued prefetch requests including N different control entries; N serial-connected translation stages for the translation of N control entries of one of the queued prefetch requests into a translated prefetch request, wherein a translation in a i-th translation stage is dependent on a translation in a (i−1)-th translation stage, iε[1, . . . , N]; and a prefetch issuer which is configured to control an index for each of the N different control entries in the prefetch queue and to issue a prefetch of the indexed control entry of the N different control entries for the highest non-stalled translation stage.
1. A method for multi-stage translation of prefetch requests, the method comprising:
providing a prefetch queue for queueing the prefetch requests, wherein each of the queued prefetch requests comprises a respective set of N control entries;
selecting a particular prefetch request of the prefetch requests;
translating, by N serial-connected translation stages, the respective set of N control entries of the particular prefetch request to obtain a translated prefetch request;
controlling a respective index corresponding to each of one or more of the N control entries;
issuing a prefetch of a particular control entry, wherein the respective index corresponding to the particular control entry is indicative of the highest non-stalled translation stage.
2. The method of claim 1 , wherein each translation stage of the N serial-connected translation stages is operatively coupled to a respective cache for caching translations.
3. The method of claim 2 , further comprising:
detecting, by a particular translation stage, a cache miss in the respective cache coupled to the particular translation stage; and
sending, to a prefetch issuer configured to issue the prefetch, an indication of a stall for the particular translation stage.
4. The method of claim 1 , wherein each of the N control entries comprises a disjunct address part of a data packet.
5. The method of claim 1 , wherein a translation in an i-th translation stage of the N serial-connected translation stages is dependent on a translation in an (i−1)-th translation stage, wherein iε[1, . . . , N].
6. The method of claim 5 , wherein the i-th translation stage is associated with at least N−i allocated conflict slots.
7. The method of claim 1 , wherein controlling the respective index corresponding to each of the one or more of the N control entries comprises controlling a set of one or more indices for prefetches for N−1 lower translation stages of the N serial-connected translation stages.
8. A device configured to perform multi-stage translation of prefetch requests, the device comprising:
a prefetch queue for queueing the prefetch requests, wherein each of the queued prefetch requests comprises a respective set of N control entries;
N serial-connected translation stages configured to translate the respective set of N control entries of a particular prefetch request to obtain a translated prefetch request; and
a prefetch issuer configured to:
control a respective index corresponding to each of one or more of the N control entries; and
issue a prefetch of a particular control entry, wherein the respective index corresponding to the particular control entry is indicative of the highest non-stalled translation stage.
9. The device of claim 8 , further comprising a respective cache operatively coupled to each translation stage of the N serial-connected translation stages for caching translations.
10. The device of claim 9 , wherein a particular translation stage is configured to:
detect a cache miss in the respective cache coupled to the particular translation stage; and
send an indication of a stall for the particular translation stage to the prefetch issuer.
11. The device of claim 8 , wherein each of the N control entries comprises a disjunct address part of a data packet.
12. The device of claim 8 , wherein a translation in an i-th translation stage of the N serial-connected translation stages is dependent on a translation in an (i−1)-th translation stage, wherein iε[1, . . . , N].
13. The device of claim 12 , wherein the i-th translation stage is associated with at least N−i allocated conflict slots.
14. The device of claim 8 , wherein the prefetch issuer is configured to control the respective index corresponding to each of the one or more of the N control entries at least in part by controlling a set of one or more indices for prefetches for N−1 lower translation stages of the N serial-connected translation stages.
15. A computer program product for multi-stage translation of prefetch requests, the computer program product comprising a non-transitory storage medium readable by a processing circuit, the storage medium storing instructions executable by the processing circuit to cause a method to be performed, the method comprising:
providing a prefetch queue for queueing the prefetch requests, wherein each of the queued prefetch requests comprises a respective set of N control entries;
selecting a particular prefetch request of the prefetch requests;
translating, by N serial-connected translation stages, the respective set of N control entries of the particular prefetch request to obtain a translated prefetch request;
controlling a respective index corresponding to each of one or more of the N control entries;
issuing a prefetch of a particular control entry, wherein the respective index corresponding to the particular control entry is indicative of the highest non-stalled translation stage.
16. The computer program product of claim 15 , wherein each translation stage of the N serial-connected translation stages is operatively coupled to a respective cache for caching translations.
17. The computer program product of claim 16 , the method further comprising:
detecting, by a particular translation stage, a cache miss in the respective cache coupled to the particular translation stage; and
sending, to a prefetch issuer configured to issue the prefetch, an indication of a stall for the particular translation stage.
18. The computer program product of claim 15 , wherein each of the N control entries comprises a disjunct address part of a data packet.
19. The computer program product of claim 15 , wherein a translation in an i-th translation stage of the N serial-connected translation stages is dependent on a translation in an (i−1)-th translation stage, wherein iε[1, . . . , N].
20. The computer program product of claim 15 , wherein controlling the respective index corresponding to each of the one or more of the N control entries comprises controlling a set of one or more indices for prefetches for N−1 lower translation stages of the N serial-connected translation stages.