IP Library › Granted Patent US 9,911,629
Granted Patent B2
US 9,911,629 · App. 15/225,083 · Granted Mar 6, 2018

Integrated passive device package and methods of forming same

Inventors: Feng-Cheng Hsu (New Taipei, TW); Shuo-Mao Chen (New Taipei, TW); Jui-Pin Hung (Hsin-Chu, TW); Shin-Puu Jeng (Hsin-Chu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L21/568H01L21/565H01L21/78H01L23/3121H01L24/02H01L24/83H01L2224/02372H01L2224/02373
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Quick Facts
Patent No.
US 9,911,629
App. No.
15/225,083
Granted
Mar 6, 2018
Kind
B2
Abstract

An embodiment device package includes a first die, a second die, and a molding compound extending along sidewalls of the first die and the second die. The package further includes redistribution layers (RDLs) extending laterally past edges of the first die and the second die. The RDLs include an input/output (I/O) contact electrically connected to the first die and the second die, and the I/O contact is exposed at a sidewall of the device package substantially perpendicular to a surface of the molding compound opposite the RDLs.

Claims (40)

1. A device package comprising:

a first die;

a second die;

a molding compound extending along sidewalls of the first die and the second die; and

redistribution layers (RDLs) extending laterally past edges of the first die and the second die, wherein the RDLs comprise an input/output (I/O) contact electrically connected to the first die and the second die, wherein the I/O contact is electrically connected to at least the first die by a conductive line, wherein a portion of the I/O contact is exposed at a sidewall of the device package, wherein an interface between the conductive line and the I/O contact extends to the sidewall of the device package, and wherein a solder region contacts the portion of the I/O contact exposed at the sidewall of the device package.

2. The device package of claim 1 , wherein the first die is an integrated passive device die substantially free of any transistors or diodes.

3. The device package of claim 1 , wherein the second die comprises a transistor, a diode, or a combination thereof.

4. The device package of claim 1 , wherein the I/O contact extends to a surface of the molding compound opposite the RDLs.

5. The device package of claim 1 , wherein the second die is adjacent the first die.

6. The device package of claim 1 , wherein the second die is disposed on an opposing side of the RDLs as the first die.

7. The device package of claim 1 , wherein all dies encapsulated by the molding compound are free of any active devices.

8. A package comprising:

a substrate;

a solder region over the substrate; and

a first device package bonded to the substrate by the solder region, wherein the first device package comprises:

a plurality of passive device dies;

a first molding compound encapsulating at least one of the plurality of passive device dies, wherein all dies encapsulated by the first molding compound are substantially free of any active regions; and

first redistribution layers (RDLs) extending laterally past edges of the plurality of passive device dies, wherein the first RDLs electrically connects the plurality of passive device dies to the substrate.

9. The package of claim 8 , wherein the first RDLs comprises a first input/output (I/O) contact exposed at a sidewall of the first device package, and wherein the solder region contacts the first I/O contact at the sidewall of the first device package.

10. The package of claim 9 , wherein the first I/O contact comprises a first surface substantially level with a second surface of the first molding compound opposite the first RDLs.

11. The package of claim 10 , wherein the solder region further contacts the first surface of the first I/O contact.

12. The package of claim 10 further comprising a second device package over the first device package and bonded to the substrate, wherein the second device package comprises:

a plurality of additional device dies;

a second molding compound encapsulating at least one of the plurality of additional device dies; and

second RDLs electrically connected to and extending laterally past edges of the plurality of additional device dies, wherein the second RDLs comprises a second I/O contact exposed at a sidewall of the second device package, and wherein a line perpendicular to the first surface of the first I/O contact intersects the second I/O contact.

13. The package of claim 12 , wherein the first I/O contact contacts the second I/O contact.

14. The package of claim 8 , wherein a first one of the plurality of passive device dies is disposed on an opposing side of the first RDLs as a second one of the plurality of passive device dies.

15. The package of claim 8 further comprising:

third RDLs disposed on an opposing side of the first molding compound as the first RDLs; and

a conductive via extending through the first molding compound and electrically connecting the third RDLs to the first RDLs.

16. A method comprising:

forming redistribution layers (RDLs) over a carrier substrate;

bonding a first die and a second die to the RDLs;

encapsulating the first die and the second die in a molding compound;

removing the carrier substrate; and

singulating the first die from the second die along a scribe line, wherein the scribe line extends through a conductive feature in the RDLs.

17. The method of claim 16 , wherein singulating the first die from the second die comprises using a singulation process in accordance with a thickness of the conductive feature.

18. The method of claim 17 , wherein the singulation process comprises mechanical dicing, laser grooving, water-assisted laser cutting, routing machining, or a combination thereof.

19. The method of claim 16 further comprising planarizing the molding compound to expose a surface of the conductive feature.

20. The method of claim 16 further comprising attaching a third die to the carrier substrate, wherein forming the RDLs comprises forming the RDLs over the third die, and wherein bonding the first die and the second die comprises bonding the first die and the second die to an opposing surface of the RDLs as the third die.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2016
From: HSU, FENG-CHENG; CHEN, SHUO-MAO; HUNG, JUI-PIN; JENG, SHIN-PUU
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 039304/0807 →
Continuity (2)
Provisional Application 62293724 · Feb 10, 2016
Related Publication 20170229322A1 · Aug 10, 2017