Embedded system boot from a storage device

1. An apparatus, comprising:

an embedded system comprising:

a processor configured to execute firmware;

a random access memory (RAM) configured to store firmware and a multi-port memory controller configured to interface with the RAM;

a power-on reset (POR) sequencer configured to control a boot process of the embedded system, wherein the POR sequence controls the boot process and verifies an integrity of loaded data and code in the RAM;

a nonvolatile memory configured to store data used by the POR sequencer in the boot process and a nonvolatile memory controller configured to interface with the nonvolatile memory;

a direct memory access (DMA) controller configured initiate and track data transfers; and

a configuration and status register (CSR) controller configured to provide an interface for the processor to access configuration and status registers of the nonvolatile memory controller, a processor bus, a CSR bus, the DMA controller, and the multi-port memory controller in the embedded system;

wherein the embedded system verifies an integrity of data and code used in the boot process and wherein the embedded system reduces an amount of the nonvolatile memory used in the boot process to provide an advantage in terms of cost and complexity.

2. The apparatus of claim 1 , further comprising:

a storage device configured to store data and code.

3. The apparatus of claim 2 , wherein the storage device comprises at least one solid state drive (SSD).

4. The apparatus of claim 1 , wherein the POR sequencer is configured to signal the nonvolatile memory controller to search for a bootstrap code loader, and wherein the processor is configured to read bootstrap code from the nonvolatile memory; and

wherein the DMA controller is configured to move firmware from the storage device to the RAM.

5. The apparatus of claim 1 , wherein the nonvolatile memory comprises a read only memory (ROM).

6. The apparatus of claim 1 , wherein the embedded system further comprises a debug interface configured to pre-program the nonvolatile memory.

7. The apparatus of claim 1 , wherein the embedded system further comprises:

a central processing unit (CPU) bus interconnecting the processor, DMA controller, multi-port memory controller, nonvolatile memory controller, and CSR controller; and

the CSR bus interconnecting the DMA controller, multi-port memory controller, nonvolatile memory controller, and CSR controller.

8. The apparatus of claim 1 , wherein the processor reads bootstrap code from the nonvolatile memory.

9. The apparatus of claim 1 , wherein the processor configures clock sources in the embedded system via the CSR bus.