Apparatus for inspecting wafer

1. A wafer inspection apparatus comprising:

a support unit configured to support a first wafer and a second wafer;

a memory having computer-readable instructions stored therein; and

at least one processor configured to execute the computer-readable instructions to cause the wafer inspection apparatus to,

derive a first polar coordinate set and a second polar coordinate set using a latin hypercube sampling such that the first and second polar coordinate sets do not overlap with each other and the first and second polar coordinate sets are distributed over an entire surface of a virtual wafer,

cause an inspection unit to perform a first defect inspection of the first wafer with respect to the first polar coordinate set and perform a second defect inspection of the second wafer with respect to the second polar coordinate set,

receive a result of the first defect inspection and a result of the second defect inspection, and combine the result of the first defect inspection with the result of the second defect inspection, and

cause to represent a result of the combination on the virtual wafer,

wherein each of the first and second polar coordinate sets is provided on a polar coordinate system that is made up of (1) a distance from an origin of the virtual wafer to the respective polar coordinates, and (2) an angle formed between a line connecting the origin of the virtual wafer with the respective polar coordinates and an X-axis.

2. The wafer inspection apparatus of claim 1 , wherein the at least one processor is further configured to cause the inspection unit is configured to perform,

the first defect inspection of the first wafer using the first polar coordinate set and a third polar coordinate set, the third polar coordinate set not overlapping the first and second polar coordinate sets, and

the second defect inspection of the second wafer using the second polar coordinate set and a fourth polar coordinate set, the fourth polar coordinate set not overlapping the first to third polar coordinates.

3. The wafer inspection apparatus of claim 1 , wherein the at least one processor is further configured to,

derive a plurality of polar coordinates using the latin hypercube sampling, and

derive the first polar coordinate set, by replacing each distance from each of the polar coordinates to the origin of the virtual wafer with a square root of a value obtained by multiplying the distance from the each of the polar coordinates to the origin of the virtual wafer by a radius of the virtual wafer.

4. The wafer inspection apparatus of claim 1 , wherein the at least one processor is further configured to,

derive three or more polar coordinate sets using the latin hypercube sampling, the three or more polar coordinate sets not overlap one another on the virtual wafer, and

inspect a plurality of wafers including the first and second wafers using the polar coordinate sets.

5. The wafer inspection apparatus of claim 4 , wherein the at least one processor are further configured to derive the three or more polar coordinate sets such that the combination of the three or more polar coordinates sets are distributed over the entire surface of the virtual wafer.

6. The wafer inspection apparatus of claim 1 , wherein the at least one processor is configured to,

set, using the latin hypercube sampling, the distance from the origin of the virtual wafer to the respective polar coordinates and an angle between the line connecting the origin of the virtual wafer with the respective polar coordinates and the X-axis on the polar coordinate system of the virtual wafer as variables, and

derive the first and second polar coordinate sets such that the first and second polar coordinates are distributed over the entire surface of the virtual wafer.

7. The wafer inspection apparatus of claim 6 , wherein the at least one processor is further configured to

select sample data in consideration of a space and the variables on the virtual wafer,

perform, a simulation using selected sample data of selected polar coordinates of the plurality of polar coordinates so that the selected polar coordinates do not overlap each other, and

obtain a respective average value and a respective deviation of result values of the simulation to derive the first and second polar coordinate sets.

8. A wafer inspection apparatus comprising:

a support unit configured to support a first wafer and a second wafer;

a memory having computer-readable instructions stored therein; and

at least one processor configured to execute the computer-readable instructions to cause the wafer inspection apparatus to,

derive a first cartesian coordinate set and a second cartesian coordinate set using a latin hypercube sampling, the first and second cartesian coordinate sets not overlapping each other, the first and second cartesian coordinate sets distributed over an entire surface of a virtual wafer, the first and second cartesian coordinate sets being sets of coordinates provided on a cartesian coordinate system made up of an X-axis and a Y-axis,

cause an inspection unit to perform a defect inspection of a first wafer using the first cartesian coordinate set,

cause the inspection unit to perform a defect inspection of a second wafer, which is different from the first wafer, using the second cartesian coordinate set, and

combine a defect inspection result of the first wafer with a defect inspection result of the second wafer.

9. The wafer inspection apparatus of claim 8 , wherein the at least one processor is further configured to

convert the first cartesian coordinate set into a first polar coordinate set,

convert the second cartesian coordinate set into a second polar coordinate set,

combine the defect inspection result of the first wafer using the first polar coordinate set with the defect inspection result of the second wafer using the second polar coordinate set, and

represent the first and second polar coordinate sets on a polar coordinate system, the polar coordinate system made up of a distance from an origin of the virtual wafer to the respective polar coordinates, and an angle formed between a line connecting the respective polar coordinates with the origin of the virtual wafer and an-X axis.

10. The wafer inspection apparatus of claim 8 , wherein the at least one processor is further configured to,

perform the defect inspection of the first wafer and a third wafer using the first cartesian coordinate set, the third wafer being different from the first and second wafers, and

perform the defect inspection of the second wafer and a fourth wafer using the second cartesian coordinate set, the fourth wafer being different from the first to third wafers.

11. The wafer inspection apparatus of claim 8 , wherein the at least one processor is further configured to,

sets, using the latin hypercube sampling, positions on the X-axis and positions on the Y-axis of the respective cartesian coordinates on the cartesian coordinate system of the virtual wafer as variables, and

derive the first and second cartesian coordinate sets such that the first and second cartesian coordinates are distributed over the entire surface of the virtual wafer.

12. The wafer inspection apparatus of claim 11 , wherein the at least one processor is further configured to,

select sample data, in consideration of a space and the variables on the virtual wafer,

perform simulations using selected sample data of selected Cartesian coordinates of the plurality of Cartesian coordinates so that the selected cartesian coordinates do not overlap each other, and

obtain average values and deviations of result values of the simulations to derive the first and second cartesian coordinate sets.

13. A wafer inspection apparatus comprising:

a memory having computer-readable instructions stored therein; and

at least one processor configured to execute the computer-readable instructions to cause the wafer inspection apparatus to,

derive a plurality of select polar coordinate sets using a latin hypercube sampling, the select polar coordinate sets not overlapping one another, the select polar coordinate sets provided on a polar coordinate system and including (1) a distance from an origin of the wafer to the respective select polar coordinates, and (2) an angle formed between a line connecting the origin of the wafer with the respective select polar coordinates and an X-axis,

inspect wafers for defects using the select polar coordinate sets, and

combine and represent defect inspection results on a virtual wafer.

14. The wafer inspection apparatus of claim 13 , wherein the at least one processor is further configured to execute the computer-readable instructions to select the polar coordinate sets to distribute substantially over an entire surface of the virtual wafer.

15. The wafer inspection apparatus of claim 13 , wherein the at least one process is further configured to execute the computer-readable instructions to cause the wafer inspection apparatus to,

select a plurality of sample polar coordinates,

simulate a plurality of polar coordinate sets using the plurality of sample polar coordinates to find a plurality of polar coordinate sets, in which polar coordinates do not overlap one another,

calculate average values and deviations with regard to the found polar coordinate sets, and

derive the plurality of select polar coordinate sets, from among the found polar coordinate sets, using the average values and the deviations such that the plurality of select polar coordinate sets cover substantially an entire surface of the virtual wafer.

16. The wafer inspection apparatus of claim 13 , wherein the at least one processor is further configured to execute the computer-readable instructions to cause the wafer inspection apparatus to derive a plurality of select polar coordinate sets by,

deriving cartesian coordinate sets using the latin hypercube sampling, and

converting the cartesian coordinate sets into the select polar coordinate sets.

17. The wafer inspection apparatus of claim 16 , wherein the at least one processor is further configured to execute the computer-readable instructions to cause the wafer inspection apparatus to,

select a plurality of sample cartesian coordinates, in consideration of a space and variables on the virtual wafer,

simulate, using the sample cartesian coordinates, the cartesian coordinates to find a plurality of cartesian coordinate sets, in which cartesian coordinates do not overlap each other,

obtain average values and deviations of result values of the found cartesian coordinates derived from the simulation; and

derive, using the average value and deviation, a plurality of select cartesian coordinate sets such that the plurality of select cartesian coordinates cover substantially an entire surface of the virtual wafer.