Clock alignment scheme for data macros of DDR PHY

1. A master-slave delay locked loop system, comprising:

a master delay locked loop (“MDLL”) for generating one or more biases; and

at least one slave delay locked loop (“SDLL”),

wherein each of the at least one SDLL has a slave calibration unit and slave delay elements,

wherein the slave calibration unit is coupled to the slave delay elements for calibrating the slave delay elements using a slave calibration loop and the generated one or more biases,

wherein the slave calibration unit comprises a coarse bias generator, a fine adjust logic, and a phase detector and control logic,

wherein the coarse bias generator and the fine adjust logic are capable of generating one or more slave biasing signals to the slave delay elements as a function of the generated one or more biases by the MDLL and a fine adjust signal generated by the phase detector and control logic,

wherein the generated one or more biases are implemented by one or more bias currents, and

wherein the fine adjust logic comprises a current digital-to-analog converter.

2. The master-slave delay locked loop system of claim 1 wherein the phase detector and control logic comprises:

bang-bang phase detector;

a sampler;

a majority logic;

an accumulator;

a first divider logic;

a second divider logic;

a sign detector; and

a code generator,

wherein the bang-bang phase detector determines a phase difference between to a zero-degree clock signal (“CK 0 ”) and a three-hundred-sixty-degree clock signal (“CK 360 ”) from the slave delay elements,

wherein the sampler, majority logic, and the accumulator generate an average phase difference between the CK 0 and CK 360 signals, and

wherein the sign detector and the code generator generate a sign and code to adjust the generated one or more biases based on the average phase difference.

3. The master-slave delay locked loop system of claim 2 wherein the first divider logic applies a divider function on the CK 360 signal to clock the sampler, majority logic, the accumulator, and the second divider logic.

4. The master-slave delay locked loop system of claim 3 wherein the second divider logic applies a divider function on the first divider logic output to clock the sign detector and the code generator.

5. A master-slave delay locked loop system, comprising:

a master delay locked loop (“MDLL”) for generating one or more bias currents; and

at least one slave delay locked loop (“SDLL”),

wherein each of the at least one SDLL has a slave calibration unit and slave delay elements,

wherein the slave calibration unit is coupled to the slave delay elements for calibrating the slave delay elements using a slave calibration loop and the generated one or more bias currents,

wherein the slave calibration unit comprises a coarse bias generator, a current digital-to-analog converter (“IDAC”) for fine adjust logic, and a phase detector and control logic, and

wherein the coarse bias generator and the IDAC are capable of generating one or more slave biasing signals to the slave delay elements as a function of the generated one or more bias currents by the MDLL and a fine adjust signal generated by the phase detector and control logic.

6. The master-slave delay locked loop system of claim 5 wherein the phase detector and control logic comprises:

bang-bang phase detector;

a sampler;

a majority logic;

an accumulator;

a first divider logic;

a second divider logic;

a sign detector; and

a code generator,

wherein the bang-bang phase detector determines a phase difference between to a zero-degree clock signal (“CK 0 ”) and a three-hundred-sixty-degree clock signal (“CK 360 ”) from the slave delay elements,

wherein the sampler, majority logic, and the accumulator generate an average phase difference between the CK 0 and CK 360 signals,

wherein the sign detector and the code generator generate a sign and code to adjust the generated one or more bias currents based on the average phase difference,

wherein the first divider logic applies a divider function on the CK 360 signal to clock the sampler, majority logic, the accumulator, and the second divider logic, and

wherein the second divider logic applies a divider function on the first divider logic output to clock the sign detector and the code generator.

7. A master-slave delay locked loop system, comprising:

a master delay locked loop (“MDLL”), wherein the MDLL generates one or more biases; and

at least one slave delay locked loop (“SDLL”),

wherein each of the at least one SDLL has a slave calibration unit and slave delay elements,

wherein the slave calibration unit calibrates the slave delay elements using a slave calibration loop and the generated one or more biases,

wherein the slave calibration unit comprises a coarse bias generator, a fine adjust logic, and a phase detector and control logic,

wherein the coarse bias generator and the fine adjust logic generate one or more slave biasing signals to the slave delay elements as a function of the generated one or more biases by the MDLL and a fine adjust signal generated by the phase detector and control logic,

wherein the phase detector and control logic comprises: bang-bang phase detector; a sampler; a majority logic; an accumulator; a first divider logic; a second divider logic; a sign detector; and a code generator,

wherein the bang-bang phase detector determines a phase difference between to a zero-degree clock signal (“CK 0 ”) and a three-hundred-sixty-degree clock signal (“CK 360 ”) from the slave delay elements,

wherein the sampler, majority logic, and the accumulator generate an average phase difference between the CK 0 and CK 360 signals,

wherein the sign detector and the code generator generate a sign and code to adjust the generated one or more biases based on the average phase difference,

wherein the first divider logic applies a divider function on the CK 360 signal to clock the sampler, majority logic, the accumulator, and the second divider logic,

wherein the second divider logic applies a divider function on the first divider logic output to clock the sign detector and the code generator,

wherein the generated one or more biases are implemented by one or more bias currents, and

wherein the fine adjust logic is a current digital-to-analog converter.