Semiconductor device testing apparatus and semiconductor device manufacturing method using it
View Patent ↗Since each wiring line is formed on one surface of the associated beam at a prescribed width over the entire length of the beam, the beam has the same sectional shape taken in the width direction at any point along an arbitrary longitudinal direction of the beam. As a result, the second moment of area, which is determined by the shapes of the beam and the wiring line, is uniform. This prevents a problem of the curvature of a beam varying locally when the beam is bent by a prescribed amount due to contact of the probe with a pad of a subject body. This, in turn, prevents local concentration of stress in the beams and thereby prevents breakage of the beam. Therefore, the probe structure can be miniaturized while the strength of the beams is kept at a required level, whereby a semiconductor device testing apparatus capable of accommodating many probes can be realized.
1. A testing apparatus having probes to be brought into contact with electrodes of a semiconductor device as a test, comprising:
a plurality of double-support beams supported by support portions of a substrate, wherein said probes are formed on said beams; and
first lines to connect said probes to secondary electrodes formed on said substrate and second lines to connect said beams to said support portions, wherein said first and second lines are formed on said beams,
wherein said first lines are formed on said substrate and are extended through through-holes formed in said support portions to connect said probes to said secondary electrodes, and said first and second lines are formed on faces of said beams when said probes are formed.
2. The testing apparatus according to claim 1 ;
wherein each said probe formed on one of said beams is distanced from and adjacent probe formed on an adjacent beam by 100 μm or less.
3. A testing apparatus according to claim 1 , wherein said beams are double-support beams, said first lines are located on a first side of said probes, and said second lines are located on another side of said probes on a front face of said double-support beams.
4. A testing apparatus according to claim 1 , wherein said secondary electrodes are formed on said substrate to face in a direction opposite to said faces of said beams where said probes are formed.
5. A testing apparatus having probes to be brought into contact with electrodes of said semiconductor device as a test, comprising:
a plurality of double-support beams that are supported by support portions of a substrate, wherein said probes are formed on said beams; and
lines to connect said probes to secondary electrodes formed on said substrate;
wherein each said line is formed on one of said double-support beams and extends from both sides of one of said probes on a face of said beam where said probe is formed,
wherein said lines are formed on said substrate and are extended through through-holes formed in said support portions to connect said probes to said secondary electrodes, and said lines are formed on faces of said beams when said probes are formed.
6. A testing apparatus for testing a semiconductor device, comprising:
a plurality of double-support beams supported by support portions of a silicon substrate;
probes that are projections formed on said beams and to be brought into contact with electrodes of said semiconductor device as a test subject; and
wiring lines that connect said probes to secondary electrodes formed on said silicon substrate, wherein said wiring lines are formed on a face of said double-support beam where said probes are formed, so as to extend to two support portions at both ends of said beam,
wherein said wiring lines are formed on said substrate and are extended through through-holes formed in said support portions to connect said probes to said secondary electrodes, and said wiring lines are formed on faces of said beams when said probes are formed.
7. A semiconductor device manufacturing method comprising;
a test process including at least one of a characteristics test process;
an initial defect accelerated selection test process; and
a final performance test process that are to be executed on LSIs formed on a wafer or individual LSIs obtained by cutting a wafer;
wherein said test process is executed by using a testing apparatus comprising:
a plurality of double-support beams supported by support portions of a silicon substrate,
probes formed on said beams and to be brought into contact with electrodes of an LSI as a test subject,
wiring lines to connect the probes to secondary electrodes formed on said silicon substrate, wherein said wiring lines are formed on a face of said double-support beams where said probes are formed and extend to said two support portions at both ends of said beam,
wherein said wiring lines are formed on said substrate and are extended through through-holes formed in said support portions to connect said probes to said secondary electrodes, and said wiring lines are formed on faces of said beams when said probes are formed.