IP Library › Patent Application 10141143
Patent Application Utility
App. No. 10/141,143 · Confirmation No. 8185

PLL CIRCUIT INCLUDING A CONTROL LOGIC CIRCUIT FOR ADJUSTING THE DELAY TIMES OF THE CLOCKS SO THAT THE PHASE ERROR OF THE CLOCKS IS REDUCED

Inventor: Yoshiaki Ito
Patent Expired Due to NonPayment of Maintenance Fees Under 37 CFR 1.362 View Patent ↗ View Publication ↗
⬇ PDF
 Code Description Pages PDF
2003-11-05 IDS Information Disclosure Statement (IDS) Form (SB08) 2 View
2003-08-26 IFEE Issue Fee Payment (PTO-85B) 1 View
2002-05-09 TRNA Transmittal of New Application 2 View
2002-05-09 ADS Application Data Sheet 2 View
2002-05-09 SPEC Specification 23 View
2002-05-09 CLM Claims 8 View
2002-05-09 ABST Abstract 1 View
2002-05-09 DRW Drawings-only black and white line drawings 11 View
2002-05-09 OATH Oath or Declaration filed 3 View
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this application's details
Quick Facts
App. No.
10/141,143
Filed
2002-05-09
Granted
2003-11-11
Pub. No.
US20030117190A1
Art Unit
2836
PTA
0 days