Method and apparatus for error handling in networks

1. A method comprising:

detecting one or more errors in a first core located within a system on a chip that has a plurality of cores and agents including the first core;

referencing a predefined classification of the first core configured at design time to determine if the first core requires isolation based on the detected one or more errors:

isolating the first core with detected errors if required by the predefined classification from other cores within that system on the chip; and

removing the first core with detected errors from isolation when the one or more errors in the first core are corrected.

2. The method of claim 1 wherein isolating the first core further comprises isolation via an agent for the first core.

3. The method of claim 2 wherein isolation via an agent for the first core is performed in hardware and

or firmware.

4. The method of claim 1 wherein detecting one or more errors in a core further comprises one or more agents not an agent for said core detecting said one or more errors in said core.

5. The method of claim 1 wherein detecting one or more errors in a core comprises determining that said core has violated a protocol used between said core and an agent for said core.

6. The method of claim 1 wherein detecting one or more errors in a core comprises determining that said core has not responded within a predetermined time period.

7. The method of claim 1 further comprising creating one or more entities associated with said one or more errors in the first core.

8. The method of claim 7 wherein said one or more entities allows access to information selected from the group consisting of command, initiator, address, and error code.

9. The method of claim 7 wherein said creating one or more entities further comprises creating one or more entries in an error log.

10. The method of claim 9 wherein said error log has a size determined from the group consisting of fixed at design time, static during operation of the first core, and dynamically variable during operation of the first core.

11. The method of claim 9 wherein said error log is located at a location selected from the group consisting of fixed at design time, static during operation of said core, dynamically variable during operation of the first core, within the first core, and external to the first core.

12. The method of claim 1 wherein the first core has a control entity allowing access to status signals and/or control signals selected from the group consisting of port lock status, busy status, reject control, clean-up control, agent status, agent reject control, agent reset, core reset, resources locked, and requests in progress.

13. The method of claim 12 wherein said agent status signal provides information selected from the group consisting of resources locked, port lock status, busy status, and requests in progress.

14. The method of claim 12 wherein said agent reject control signal when asserted causes an agent to reject new requests to said agent.

15. The method of claim 12 wherein said agent reset and said core reset signal when asserted causes a respective agent and said core to be reset without affecting other than said respective agent and core.

16. A processing system comprising a processor, which when executing a set of instructions causes the processing system to perform the method of claim 1 .

17. A machine-readable medium having stored thereon instructions, which when executed causes a machine to perform the method of claim 1 .

18. An apparatus comprising:

a plurality of cores located within a system on a chip, each core having a communication link;

a plurality of agents located within that system on the chip, each agent having a first link and a second link, the first link of each agent coupled to a respective communication link of a specific core, the second link of each agent coupled to the second link of other agents via a network; and

an error reporting agent having an input and an output, the input coupled to said network, and the output coupled to transmit a signal, wherein the error reporting agent to isolate a first core with detected errors, if required by a predefined classification determined at design time, from other cores within that system on the chip by sending a signal to a first agent to no longer accept new requests from a first core coupled to the first link of the first agent or accept requests from other agents located within that system on the chip, which couple to the second link of the first agent.

19. The apparatus of claim 18 wherein said signal is an error signal indicating a condition selected from the group consisting of that one or more of said plurality of cores has been isolated, that one or more of said plurality of cores has an error, and that an error has occurred in said network.

20. The apparatus of claim 18 wherein each core is predefined as a reliable or non-reliable core based on the predefined classification determined at design time.

21. An method comprising:

configuring a plurality of cores located within a system on a chip, each of said cores connected with and associated with each of one of a plurality of initiators;

connecting one or more of said plurality of initiators to a network located within said system on the chip;

one or more of said plurality of initiators to determine an error in one or more said cores;

communicating said error to the other initiators located within said system on the; chip; isolating one or more cores based on said error, if required by a predefined classification determined at design time;

storing information related to said error;

controlling said one or more isolated cores; and

removing said one or more isolated cores from isolation when said error is corrected.

22. A machine-readable medium having stored thereon instructions, which when executed, to generate a representation of an apparatus to perform the method of claim 21 .

23. A method comprising;

receiving a timeout request from an initiator;

determining if said timeout request is targeted to a reliable or unreliable core based on a predefined classification determined at design time located within a system on a chip; and

if targeted to a reliable core

sending a timeout non-acknowledgement to said timeout request and

proceeding normally;

else

sending a timeout acknowledgement to said timeout request,

isolating said core from other cores within that system on the chip, and

removing said core from isolation when one or more errors in said core are corrected.

24. The method of claim 23 wherein said reliable or unreliable core is determined at a point in time prior to operation of said reliable or unreliable core.