Multi-standard variable block size motion estimation processor
View Patent ↗An apparatus generally having a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to generate a plurality of difference values by calculating an absolute difference between each pixel from a current block and a corresponding pixel from a reference block substantially simultaneously. The second circuit may be configured to generate a plurality of sum values by adding the difference values. The third circuit may be configured to generate at least one motion vector in response to the sum values.
1. An apparatus comprising:
a first circuit configured to generate a plurality of difference values by calculating an absolute difference between each pixel from a current block and a corresponding pixel from a reference block substantially simultaneously;
a second circuit configured to generate a plurality of sum values by adding said difference values; and
a third circuit configured to generate (i) a mode signal identifying a best mode among at least four partition modes, (ii) a motion signal conveying at least one motion vector associated with said best mode and (iii) a score signal conveying a score value associated with said best mode all in response to said sum values, wherein said third circuit comprises (i) an adder circuit configured to generate a plurality of first intermediate values from said sum values, (ii) a storage circuit configured to generate a plurality of second intermediate values from said first intermediate values as said current block is moved through a search window, (iii) a select circuit configured to generate (a) said mode signal, (b) said motion signal and (c) said score signal all from said second intermediate values, and (iv) a first bias circuit configured to generate a cost value based on all of (a) a quantization parameter and (b) a motion vector magnitude and wherein said storage circuit is further configured to add said cost value to each of said first intermediate values.
2. The apparatus according to claim 1 , wherein said first circuit comprises a plurality of processing elements each configured to generate one of said difference values.
3. The apparatus according to claim 2 , wherein said processing elements are logically configured as a two-dimensional array receiving said pixels from said current block and said reference block on a first side of said array and presenting said difference values on a second side of said array.
4. The apparatus according to claim 1 , wherein said second circuit comprises a plurality of adder circuits each configured to generate one of said sum values substantially simultaneously by adding a unique combination of said difference values.
5. The apparatus according to claim 1 , wherein each of said first intermediate values corresponds to one of said partition modes of said current block.
6. The apparatus according to claim 1 , wherein each of said sum values corresponds to a smallest partition among said partition modes of said current block.
7. The apparatus according to claim 1 , wherein (i) said third circuit further comprises a second bias circuit configured to generate a plurality of bias values based on said quantization parameter and (ii) said storage circuit is further configured to add each one of said bias values to a respective one of said second intermediate values.
8. A method for motion estimation, comprising the steps of:
(A) generating a plurality of difference values by calculating an absolute difference between each pixel from a current block and a corresponding pixel from a reference block substantially simultaneously;
(B) generating a plurality of sum values by adding said difference values;
(C) generating a mode signal identifying a best mode among at least four partition modes in response to said sum values;
(D) generating a motion signal conveying at least one motion vector associated with said best mode in response to said sum values;
(E) generating a score signal conveying a score value associated with said best mode in response to said sum values;
(F) generating a plurality of first intermediate values from said sum values, one of said intermediate values corresponding to each of said partition modes of said current block;
(G) generating a cost value based on all of (i) a quantization parameter and (ii) a motion vector magnitude; and
(H) adding said cost value to each of said first intermediate values.
9. The method according to claim 8 , further comprising the step of:
generating a plurality of minimum values by retaining a smallest of said sum values corresponding to each of said first intermediate values as said current block is moved through a search window.
10. The method according to claim 9 , further comprising the step of:
generating a plurality of second intermediate values by adding a plurality of bias values to said minimum values.
11. The method according to claim 10 , wherein step (D) further comprises the sub-step of:
generating said motion signal by determining a best of said second intermediate values.
12. The method according to claim 10 , wherein said bias values are generated based on a quantization parameter.
13. The method according to claim 8 , further comprising the step of:
generating a first subset of a plurality of first intermediate values by adding a first group said difference values in a plurality of unique combinations.
14. A circuit comprising:
means for generating a plurality of difference values by calculating an absolute difference between each pixel from a current block and a corresponding pixel from a reference block substantially simultaneously;
means for generating a plurality of sum values by adding said difference values substantially simultaneously; and
means for generating (i) a mode signal identifying a best mode among at least four partition modes, (ii) a motion signal conveying at least one motion vector associated with said best mode and (iii) a score signal conveying a score value associated with said best mode all in response to said sum values, wherein said third circuit comprises (i) an adder circuit configured to generate a plurality of first intermediate values from said sum values, (ii) a storage circuit configured to generate a plurality of second intermediate values from said first intermediate values as said current block is moved through a search window, and (iii) a select circuit configured to generate (i) said mode signal, (ii) said motion signal and (iii) said score signal all from said second intermediate values, and (iv) a first bias circuit configured to generate a cost value based on all of (a) a quantization parameter and (b) a motion vector magnitude and wherein said storage circuit is further configured to add said cost value to each of said first intermediate values.
15. An apparatus comprising:
a first circuit configured to generate a plurality of difference values by calculating an absolute difference between each pixel from a current block and a corresponding pixel from a reference block substantially simultaneously;
a second circuit configured to generate a plurality of sum values by adding said difference values; and
a third circuit configured to generate (i) a mode signal identifying a best mode among at least four partition modes, (ii) a motion signal conveying at least one motion vector associated with said best mode and (iii) a score signal conveying a score value associated with said best mode all in response to said sum values, wherein said third circuit comprises (i) an adder circuit configured to generate a plurality of first intermediate values from said sum values, (ii) a storage circuit configured to generate a plurality of second intermediate values from said first intermediate values as said current block is moved through a search window, and (iii) a select circuit configured to generate (a) said mode signal, (b) said motion signal and (c) said score signal all from said second intermediate values and wherein said second circuit is further configured to generate (i) a plurality of minimum values by retaining a smallest of said sum values corresponding to each of said first intermediate values and (ii) generate said second intermediate values by adding a plurality of bias values to said minimum values.
16. The method according to claim 13 , wherein a second subset of said first intermediate values comprises a second group of said sum values.