Stratum clock state machine multiplexing switching
View Patent ↗A method includes receiving a pair of input clock signals; utilizing a stratum clock state machine to control a multiplexer; utilizing the multiplexer to switch an input of a main clock between each of the pair of input clock signals; inducing a phase build-out activity; and transmitting an output clock signal.
1. A method, comprising:
receiving a pair of input clock signals;
utilizing a stratum clock state machine to control a multiplexer;
utilizing the multiplexer to switch an input of a main clock between each of the pair of input clock signals;
inducing a phase build-out activity except when a skip timer is loaded; and
transmitting an output clock signal,
wherein a main clock phase lock loop which receives the main clock is allowed to adjust without the phase build-out activity occurring when the skip timer is loaded and a frequency offset signal is asserted.
2. The method of claim 1 , wherein inducing the phase build-out activity includes eliminating a set of input transients.
3. The method of claim 1 , further comprising utilizing the stratum clock state machine to manage a plurality of phase-locked loops.
4. The method of claim 1 , further comprising utilizing the stratum clock state machine to set the main clock to a main clock phase lock loop normal state.
5. The method of claim 1 , further comprising utilizing the stratum clock state machine set to the main clock phase lock loop to a main clock freerun state.
6. The method of claim 1 , further comprising utilizing the stratum clock state machine to set the main clock phase lock loop to a main clock holdover state.
7. The method of claim 1 , further comprising setting the stratum clock state machine in a state including at least one member selected from the group consisting of: a stratum clock state machine normal state, a stratum clock state machine freerun state, a stratum clock state machine switch state, a stratum clock state machine offset state and a stratum clock state machine holdover state.
8. A computer program, comprising computer or machine readable program elements translatable for implementing a method including:
receiving a pair of input clock signals;
utilizing a stratum clock state machine to control a multiplexer;
utilizing the multiplexer to switch an input of a main clock between each of the pair of input clock signals;
inducing a phase build-out activity except when a skip timer is loaded; and
transmitting an output clock signal,
wherein a main clock phase lock loop which receives the main clock is allowed to adjust without the phase build-out activity occurring when the skip timer is loaded and a frequency offset signal is asserted.