IP Library Granted Patent US 7,125,794
Granted Patent B2
US 7,125,794 · App. 10/940,820 · Granted Oct 24, 2006

Method of manufacturing semiconductor device

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Quick Facts
Patent No.
US 7,125,794
App. No.
10/940,820
Granted
Oct 24, 2006
Kind
B2
Abstract

A first CVD dielectric layer is deposited on a surface of a semiconductor substrate. Next, low-k layers are deposited in at least two different steps to form one of a via-layer dielectric film and a wiring-layer dielectric film on the first CVD dielectric layer. Immediately after the depositions, thermal treatment is performed. A second CVD dielectric layer is deposited on the low-k layers. A groove is formed in the second CVD dielectric layer and the low-k layers. A metal layer is deposited on that structure, filling the groove. The metal layer is removed from the second CVD dielectric layer by chemical mechanical polishing.

Claims (16)

1. A method of manufacturing a semiconductor device comprising:

depositing a first CVD dielectric layer on a surface of a semiconductor substrate;

depositing a first low-k layer on the first CVD dielectric layer from source materials and, immediately after depositing the first low-k layer, thermally treating the first low-k layer;

depositing a second low-k layer on the first low-k layer from the same source materials used to deposit the first low-k layer and, immediately after depositing the second low-k layer, thermally treating the second low-k layer;

depositing a second CVD dielectric layer on the second low-k layer;

forming a groove in the second CVD dielectric layer, the second low-k layer, and the first low-k layer;

depositing a metal layer on the second CVD dielectric layer and filling the groove; and

removing the metal layer from the second CVD dielectric layer by chemical mechanical polishing.

2. The method of manufacturing a semiconductor device according to claim 1 , including thermally treating the first and second low-k layers at temperatures of at least 100° C. and no more than 500° C.

3. The method of manufacturing a semiconductor device according to claim 1 , including using a methyl silsesquioxane resin as the first and second low-k layers.

4. The method of manufacturing a semiconductor device according to claim 1 , as including depositing as the first and second low-k layers, low-k layers having a composition ratio of silicon:oxygen:carbon=20% to 40%:40% to 60%:10% to 30%.

5. The method of manufacturing a semiconductor device according to claim 1 , further comprising plasma treating after depositing the second low-k layer.

6. The method of manufacturing a semiconductor device according to claim 1 , wherein the metal layer is a wiring layer and the first and second low-k layers are wiring dielectric films at a side of the wiring layer, on the substrate.

7. The method of manufacturing a semiconductor device according to claim 1 , including depositing the first and second low-k layers by spin coating.

8. The method of manufacturing a semiconductor device according to claim 1 , including thermally treating the first and second low-k layers in a nitrogen ambient.

9. The method of manufacturing a semiconductor device according to claim 1 , wherein thermally treating both of the first and second low-k layers includes thermally treating each of the first and second low-k layers at each of two different temperatures.

Assignments (4)
CHANGE OF NAME Recorded Sep 8, 2010
From: RENESAS TECHNOLOGY CORP.
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024953/0224 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2005
From: SEMICONDUCTOR LEADING EDGE TECHNOLOGIES, INC.
To: RENESAS TECHNOLOGY CORP.
Reel/Frame 016206/0616 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S ADDRESS, PREVIOUSLY RECORDED AT REEL 015802 FRAME 0328. Recorded Mar 29, 2005
From: KONDO, SEIICHI; MISAWA, KAORI; TOKITOH, SHUNICHI; NASUNO, TAKASHI
To: SEMICONDUCTOR LEADING EDGE TECHNOLOGIES, INC.
Reel/Frame 016406/0293 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 15, 2004
From: KONDO, SEIICHI; MISAWA, KAORI; TOKITOH, SHUNICHI; NASUNO, TAKASHI
To: SEMICONDUCTOR LEADING EDGE TECHNOLOGIES, INC.
Reel/Frame 015802/0328 →